f08f0cafc2
Update the HSSPI driver with the upstream submitted one that has a workaround for the auto cs down issue. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39264
36 lines
914 B
Diff
36 lines
914 B
Diff
From c8b7d2630d907025ce30989bddd01f4f0f13c103 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Wed, 20 Nov 2013 17:22:40 +0100
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Subject: [PATCH 2/5] MIPS: BCM63XX: setup the HSSPI clock rate
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Properly set up the HSSPI clock rate depending on the SoC's PLL rate.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/clk.c | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -378,3 +378,21 @@ void clk_put(struct clk *clk)
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}
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EXPORT_SYMBOL(clk_put);
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+
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+#define HSSPI_PLL_HZ_6328 133333333
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+#define HSSPI_PLL_HZ_6362 400000000
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+
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+static int __init bcm63xx_clk_init(void)
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+{
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+ switch (bcm63xx_get_cpu_id()) {
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+ case BCM6328_CPU_ID:
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+ clk_hsspi.rate = HSSPI_PLL_HZ_6328;
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+ break;
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+ case BCM6362_CPU_ID:
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+ clk_hsspi.rate = HSSPI_PLL_HZ_6362;
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+ break;
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+ }
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+
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+ return 0;
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+}
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+arch_initcall(bcm63xx_clk_init);
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