69d323f231
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.10, and Linux v3.11. This work mainly covers: * Enabling USB storage, and PCI to mvebu_defconfig. * Add support for NOR flash. * Some PCI device tree related updates, and bus parsing. * Adding Armada XP & 370 PCI driver, and update some clock gating specifics. * Introduce Marvell EBU Device Bus driver. * Enaling USB in the armada*.dts. * Enabling, and updating the mvebu-mbus. * Some SATA and Ethernet related fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39564
91 lines
3.2 KiB
Diff
91 lines
3.2 KiB
Diff
From 71a32c9519ba223d1dafcbe58d1699710720c5a8 Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 1 Aug 2013 15:44:19 +0200
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Subject: [PATCH 036/203] PCI: mvebu: Disable prefetchable memory support in
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PCI-to-PCI bridge
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The Marvell PCIe driver uses an emulated PCI-to-PCI bridge to be able
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to dynamically set up MBus address decoding windows for PCI I/O and
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memory regions depending on the PCI devices enumerated by Linux.
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However, this emulated PCI-to-PCI bridge logic makes the Linux PCI
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core believe that prefetchable memory regions are supported (because
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the registers are read/write), while in fact no adress decoding window
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is ever created for such regions. Since the Marvell MBus address
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decoding windows do not distinguish memory regions and prefetchable
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memory regions, this patch takes a simple approach: change the
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PCI-to-PCI bridge emulation to let the Linux PCI core know that we
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don't support prefetchable memory regions.
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To achieve this, we simply make the prefetchable memory base a
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read-only register that always returns 0. Reading/writing all the
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other prefetchable memory related registers has no effect.
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This problem was originally reported by Finn Hoffmann
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<finn@uni-bremen.de>, who couldn't get a RTL8111/8168B PCI NIC working
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on the NSA310 Kirkwood platform after updating to 3.11-rc. The problem
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was that the PCI-to-PCI bridge emulation was making the Linux PCI core
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believe that we support prefetchable memory, so the Linux PCI core was
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only filling the prefetchable memory base and limit registers, which
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does not lead to a MBus window being created. The below patch has been
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confirmed by Finn Hoffmann to fix his problem on Kirkwood, and has
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otherwise been successfully tested on the Armada XP GP platform with a
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e1000e PCIe NIC and a Marvell SATA PCIe card.
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Reported-by: Finn Hoffmann <finn@uni-bremen.de>
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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---
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drivers/pci/host/pci-mvebu.c | 27 +--------------------------
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1 file changed, 1 insertion(+), 26 deletions(-)
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--- a/drivers/pci/host/pci-mvebu.c
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+++ b/drivers/pci/host/pci-mvebu.c
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@@ -86,10 +86,6 @@ struct mvebu_sw_pci_bridge {
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u16 secondary_status;
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u16 membase;
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u16 memlimit;
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- u16 prefmembase;
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- u16 prefmemlimit;
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- u32 prefbaseupper;
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- u32 preflimitupper;
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u16 iobaseupper;
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u16 iolimitupper;
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u8 cappointer;
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@@ -419,15 +415,7 @@ static int mvebu_sw_pci_bridge_read(stru
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break;
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case PCI_PREF_MEMORY_BASE:
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- *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
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- break;
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-
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- case PCI_PREF_BASE_UPPER32:
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- *value = bridge->prefbaseupper;
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- break;
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-
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- case PCI_PREF_LIMIT_UPPER32:
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- *value = bridge->preflimitupper;
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+ *value = 0;
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break;
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case PCI_IO_BASE_UPPER16:
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@@ -501,19 +489,6 @@ static int mvebu_sw_pci_bridge_write(str
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mvebu_pcie_handle_membase_change(port);
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break;
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- case PCI_PREF_MEMORY_BASE:
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- bridge->prefmembase = value & 0xffff;
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- bridge->prefmemlimit = value >> 16;
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- break;
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-
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- case PCI_PREF_BASE_UPPER32:
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- bridge->prefbaseupper = value;
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- break;
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-
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- case PCI_PREF_LIMIT_UPPER32:
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- bridge->preflimitupper = value;
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- break;
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-
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case PCI_IO_BASE_UPPER16:
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bridge->iobaseupper = value & 0xffff;
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bridge->iolimitupper = value >> 16;
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