25afe99b31
the support is still WIP. next steps are to make the pmic and ethernet work. this is the first commit to make sure nothing gets lost. Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 47354
47 lines
1.7 KiB
Diff
47 lines
1.7 KiB
Diff
From 908a87b47af8303c9aa8fb6aa183ca9f8b544d78 Mon Sep 17 00:00:00 2001
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From: YH Huang <yh.huang@mediatek.com>
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Date: Mon, 11 May 2015 17:26:21 +0800
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Subject: [PATCH 27/76] dt-bindings: pwm: add Mediatek display PWM bindings
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Document the device-tree binding of Mediatek display PWM.
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Signed-off-by: YH Huang <yh.huang@mediatek.com>
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---
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.../devicetree/bindings/pwm/pwm-disp-mediatek.txt | 25 ++++++++++++++++++++
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1 file changed, 25 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt
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diff --git a/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt
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new file mode 100644
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index 0000000..ef54e9d
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt
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@@ -0,0 +1,25 @@
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+Mediatek display PWM controller
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+
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+Required properties:
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+ - compatible: should be "mediatek,<name>-disp-pwm"
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+ - "mediatek,mt8173-disp-pwm": found on mt8173 SoC
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+ - "mediatek,mt6595-disp-pwm": found on mt6595 SoC
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+ - reg: physical base address and length of the controller's registers
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+ - #pwm-cells: must be 2. See pwm.txt in this directory
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+ for a description of the cell format
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+ - clocks: phandle and clock specifier of the PWM reference clock
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+ - clock-names: must contain the following
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+ - "main": clock used to generate PWM signals
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+ - "mm": sync signals from the modules of mmsys
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+
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+Example:
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+ pwm0: pwm@1401e000 {
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+ compatible = "mediatek,mt8173-disp-pwm",
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+ "mediatek,mt6595-disp-pwm";
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+ reg = <0 0x1401e000 0 0x1000>;
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+ #pwm-cells = <2>;
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+ clocks = <&mmsys MM_DISP_PWM026M>,
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+ <&mmsys MM_DISP_PWM0MM>;
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+ clock-names = "main",
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+ "mm";
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+ };
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--
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1.7.10.4
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