119 lines
3.6 KiB
Diff
119 lines
3.6 KiB
Diff
From 5ca9eadcb5f5cd9af6f1650029ad64052a1a0b10 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Tue, 24 Dec 2013 21:26:17 +0800
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Subject: [PATCH] clk: sunxi: Allwinner A20 output clock support
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This patch adds support for the external clock outputs on the
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Allwinner A20 SoC. The clock outputs are similar to "module 0"
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type clocks, with different offsets and widths for clock factors.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
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drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
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2 files changed, 58 insertions(+)
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diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
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index 941bd93..79c7197 100644
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -36,6 +36,7 @@ Required properties:
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"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
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+ "allwinner,sun7i-a20-out-clk" - for the external output clocks
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index 8a07a68..df1f385 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -396,6 +396,47 @@ void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
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/**
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+ * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
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+ * CLK_OUT rate is calculated as follows
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+ * rate = (parent_rate >> p) / (m + 1);
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+ */
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+
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+static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
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+ u8 *n, u8 *k, u8 *m, u8 *p)
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+{
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+ u8 div, calcm, calcp;
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+
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+ /* These clocks can only divide, so we will never be able to achieve
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+ * frequencies higher than the parent frequency */
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+ if (*freq > parent_rate)
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+ *freq = parent_rate;
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+
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+ div = parent_rate / *freq;
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+
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+ if (div < 32)
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+ calcp = 0;
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+ else if (div / 2 < 32)
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+ calcp = 1;
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+ else if (div / 4 < 32)
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+ calcp = 2;
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+ else
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+ calcp = 3;
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+
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+ calcm = DIV_ROUND_UP(div, 1 << calcp);
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+
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+ *freq = (parent_rate >> calcp) / calcm;
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+
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+ /* we were called to round the frequency, we can now return */
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+ if (n == NULL)
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+ return;
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+
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+ *m = calcm - 1;
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+ *p = calcp;
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+}
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+
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+
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+
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+/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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@@ -455,6 +496,14 @@ struct factors_data {
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.pwidth = 2,
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};
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+/* user manual says "n" but it's really "p" */
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+static struct clk_factors_config sun7i_a20_out_config = {
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+ .mshift = 8,
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+ .mwidth = 5,
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+ .pshift = 20,
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+ .pwidth = 2,
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+};
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+
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static const struct factors_data sun4i_pll1_data __initconst = {
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.enable = 31,
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.table = &sun4i_pll1_config,
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@@ -492,6 +541,13 @@ struct factors_data {
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.getter = sun4i_get_mod0_factors,
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};
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+static const struct factors_data sun7i_a20_out_data __initconst = {
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+ .enable = 31,
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+ .mux = 24,
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+ .table = &sun7i_a20_out_config,
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+ .getter = sun7i_a20_get_out_factors,
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+};
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+
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static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
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const struct factors_data *data)
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{
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@@ -995,6 +1051,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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{.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
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{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
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{.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
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+ {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
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{}
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};
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--
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1.8.5.1
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