65 lines
1.8 KiB
Diff
65 lines
1.8 KiB
Diff
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
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index dd620c1..15b4a03 100644
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--- a/drivers/mtd/nand/nand_ids.c
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+++ b/drivers/mtd/nand/nand_ids.c
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@@ -19,6 +19,49 @@
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#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
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/*
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+ * Hynix H27UBG8T2BTR timings
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+ * This chip has an exceptionally large tADL, which results in only supporting
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+ * ONFI timing mode 0. Using these timings, the clock can be raised from
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+ * 12.5MHz to 50MHz.
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+ */
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+const struct nand_sdr_timings hynix_h27ubg8t2btr_sdr_timing = {
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+ .tADL_min = 200000,
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+ .tALH_min = 5000,
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+ .tALS_min = 10000,
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+ .tAR_min = 10000,
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+ .tCEA_max = 100000,
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+ .tCEH_min = 20000,
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+ .tCH_min = 5000,
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+ .tCHZ_max = 50000,
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+ .tCLH_min = 5000,
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+ .tCLR_min = 10000,
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+ .tCLS_min = 10000,
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+ .tCOH_min = 15000,
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+ .tCS_min = 20000,
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+ .tDH_min = 5000,
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+ .tDS_min = 10000,
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+ .tFEAT_max = 1000000,
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+ .tIR_min = 0,
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+ .tITC_max = 1000000,
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+ .tRC_min = 20000,
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+ .tREA_max = 16000,
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+ .tREH_min = 8000,
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+ .tRHOH_min = 15000,
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+ .tRHW_min = 100000,
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+ .tRHZ_max = 100000,
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+ .tRLOH_min = 5000,
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+ .tRP_min = 10000,
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+ .tRST_max = 500000000,
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+ .tWB_max = 100000,
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+ .tRR_min = 20000,
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+ .tWC_min = 20000,
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+ .tWH_min = 10000,
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+ .tWHR_min = 80000,
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+ .tWP_min = 8000,
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+ .tWW_min = 100000,
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+};
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+
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+/*
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* The chip ID list:
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* name, device ID, page size, chip size in MiB, eraseblock size, options
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*
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@@ -50,6 +93,10 @@ struct nand_flash_dev nand_flash_ids[] = {
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{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
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SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
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4 },
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+ {"H27UBG8T2BTR-BC 64G 3.3V 8-bit",
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+ { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
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+ SZ_8K, SZ_4K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
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+ 0, &hynix_h27ubg8t2btr_sdr_timing },
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LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
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