70 lines
2.2 KiB
Diff
70 lines
2.2 KiB
Diff
From 3fecbdac2fe503fb6896ec08dd2474958d198d62 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Sun, 24 May 2015 12:01:16 +0200
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Subject: [PATCH] mtd: nand: nand_decode_ext_id(): Fill in ecc strength and
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size for Samsung
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On some nand controllers with hw-ecc the controller code wants to know the
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ecc strength and size and having these as 0, 0 is not accepted.
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Specifying these in devicetree is possible but undesirable as the nand
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may be different in different production runs of the same board, so it
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is better to get this info from the nand id where possible.
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This commit adds code to read the ecc strength and size from the nand for
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Samsung extended-id nands. This code is based on the info for the 5th
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id byte in the datasheets for the following Samsung nands: K9GAG08U0E,
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K9GAG08U0F, K9GAG08X0D, K9GBG08U0A, K9GBG08U0B. These all use these bits
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in the exact same way.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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drivers/mtd/nand/nand_base.c | 35 +++++++++++++++++++++++++++++++++++
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1 file changed, 35 insertions(+)
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diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
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index 51642c6..e3d4d8e 100644
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--- a/drivers/mtd/nand/nand_base.c
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+++ b/drivers/mtd/nand/nand_base.c
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@@ -4063,6 +4063,41 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
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mtd->erasesize = (128 * 1024) <<
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(((extid >> 1) & 0x04) | (extid & 0x03));
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*busw = 0;
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+ /* Calc ecc strength and size from 5th id byte*/
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+ switch ((id_data[4] >> 4) & 0x07) {
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+ case 0:
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+ chip->ecc_strength_ds = 1;
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+ chip->ecc_step_ds = 512;
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+ break;
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+ case 1:
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+ chip->ecc_strength_ds = 2;
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+ chip->ecc_step_ds = 512;
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+ break;
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+ case 2:
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+ chip->ecc_strength_ds = 4;
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+ chip->ecc_step_ds = 512;
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+ break;
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+ case 3:
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+ chip->ecc_strength_ds = 8;
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+ chip->ecc_step_ds = 512;
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+ break;
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+ case 4:
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+ chip->ecc_strength_ds = 16;
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+ chip->ecc_step_ds = 512;
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+ break;
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+ case 5:
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+ chip->ecc_strength_ds = 24;
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+ chip->ecc_step_ds = 1024;
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+ break;
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+ case 6:
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+ chip->ecc_strength_ds = 40;
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+ chip->ecc_step_ds = 1024;
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+ break;
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+ case 7:
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+ chip->ecc_strength_ds = 60;
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+ chip->ecc_step_ds = 1024;
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+ break;
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+ }
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} else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
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!nand_is_slc(chip)) {
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unsigned int tmp;
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