c7bf2accc9
These are cherry-picked & backported from LKML: *https://lkml.org/lkml/2015/3/17/19 They are enabled on both 3.18 and 4.1 kernel. Patches 150 to 154 are applying changes merged since 3.18; they enable mechanisms used by the ADM driver. ADM engine is used by the NAND controller, so it is necessary to bring-up NAND flash support. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46567
54 lines
1.4 KiB
Diff
54 lines
1.4 KiB
Diff
From 1fb18acab2d71e7e4efd9c10492edb1baf84dcc0 Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Wed, 20 May 2015 15:41:07 +0530
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Subject: [PATCH] ARM: DT: ipq8064: Add ADM device node
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This patch adds support for the ADM DMA on the IPQ8064 SOC
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 4 ++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 21 +++++++++++++++++++++
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2 files changed, 25 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -90,6 +90,10 @@
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cs-gpios = <&qcom_pinmux 20 0>;
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+ dmas = <&adm_dma 6>,
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+ <&adm_dma 5>;
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+ dma-names = "rx", "tx";
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+
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flash: m25p80@0 {
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compatible = "s25fl256s1";
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#address-cells = <1>;
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -657,5 +657,25 @@
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};
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};
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+ adm_dma: dma@18300000 {
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+ compatible = "qcom,adm";
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+ reg = <0x18300000 0x100000>;
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+ interrupts = <0 170 0>;
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+ #dma-cells = <1>;
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+
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+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
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+ clock-names = "core", "iface";
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+
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+ resets = <&gcc ADM0_RESET>,
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+ <&gcc ADM0_PBUS_RESET>,
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+ <&gcc ADM0_C0_RESET>,
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+ <&gcc ADM0_C1_RESET>,
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+ <&gcc ADM0_C2_RESET>;
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+ reset-names = "clk", "pbus", "c0", "c1", "c2";
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+ qcom,ee = <0>;
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+
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+ status = "disabled";
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+ };
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+
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};
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};
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