28 lines
767 B
C
28 lines
767 B
C
/*
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* HND SiliconBackplane MIPS/ARM cores software interface.
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*
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* Copyright 2006, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
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*/
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#ifndef _hndcpu_h_
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#define _hndcpu_h_
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#if defined(mips)
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#include <hndmips.h>
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#elif defined(__ARM_ARCH_4T__)
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#include <hndarm.h>
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#endif
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extern uint sb_irq(sb_t *sbh);
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extern uint32 sb_cpu_clock(sb_t *sbh);
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extern void sb_cpu_wait(void);
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#endif /* _hndcpu_h_ */
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