38 lines
1.4 KiB
Diff
38 lines
1.4 KiB
Diff
PCI: imx6: fix occasional link failure
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According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
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for SS function) must remain deasserted until the reference clock is running
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at the appropriate frequency.
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Without this patch we find a high link failure rate (>5%) on certain
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IMX6 boards at various temperatures.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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--- a/drivers/pci/host/pci-imx6.c
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -262,11 +262,6 @@ static int imx6_pcie_deassert_core_reset
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if (gpio_is_valid(imx6_pcie->power_on_gpio))
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gpio_set_value(imx6_pcie->power_on_gpio, 1);
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- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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- IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
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- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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- IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
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-
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ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
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if (ret) {
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dev_err(pp->dev, "unable to enable sata_ref_100m\n");
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@@ -294,6 +289,12 @@ static int imx6_pcie_deassert_core_reset
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/* allow the clocks to stabilize */
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usleep_range(200, 500);
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+ /* power up core phy and enable ref clock */
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+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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+ IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
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+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
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+
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/* Some boards don't have PCIe reset GPIO. */
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if (gpio_is_valid(imx6_pcie->reset_gpio)) {
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gpio_set_value(imx6_pcie->reset_gpio, 0);
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