3c1f6e358d
Patches are generated using the "format-patch" command from the following location: *https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base *rev=0771849495b4128cac2faf7d49c85c729fc48b20 Patches numbered 76/77/102/103 have already been integrated in 3.14.12, so they're not in this list. All these patches are either integrated are pending integration into kernel.org, therefore these patches should go away once the kernel gets upgraded to 3.16. Support is currently limited to AP148 board but can be extended to other platforms in the future. These changes do not cover ethernet connectivity. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 42334
172 lines
4.3 KiB
Diff
172 lines
4.3 KiB
Diff
From eb07c23d45ddf10fa89296e6c6c6aed553d8bbf5 Mon Sep 17 00:00:00 2001
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From: Rohit Vaswani <rvaswani@codeaurora.org>
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Date: Fri, 21 Jun 2013 17:09:13 -0700
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Subject: [PATCH 014/182] ARM: qcom: Add SMP support for KPSSv2
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Implement support for the Krait CPU release sequence when the
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CPUs are part of the second version of the Krait processor
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subsystem.
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Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/mach-qcom/platsmp.c | 123 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 123 insertions(+)
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diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
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index cb0783f..d690856 100644
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--- a/arch/arm/mach-qcom/platsmp.c
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+++ b/arch/arm/mach-qcom/platsmp.c
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@@ -34,7 +34,15 @@
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#define L2DT_SLP BIT(3)
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#define CLAMP BIT(0)
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+#define APC_PWR_GATE_CTL 0x14
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+#define BHS_CNT_SHIFT 24
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+#define LDO_PWR_DWN_SHIFT 16
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+#define LDO_BYP_SHIFT 8
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+#define BHS_SEG_SHIFT 1
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+#define BHS_EN BIT(0)
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+
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#define APCS_SAW2_VCTL 0x14
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+#define APCS_SAW2_2_VCTL 0x1c
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extern void secondary_startup(void);
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@@ -160,6 +168,106 @@ out_acc:
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return ret;
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}
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+static int kpssv2_release_secondary(unsigned int cpu)
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+{
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+ void __iomem *reg;
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+ struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
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+ void __iomem *l2_saw_base;
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+ unsigned reg_val;
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+ int ret;
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+
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+ cpu_node = of_get_cpu_node(cpu, NULL);
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+ if (!cpu_node)
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+ return -ENODEV;
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+
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+ acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
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+ if (!acc_node) {
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+ ret = -ENODEV;
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+ goto out_acc;
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+ }
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+
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+ l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
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+ if (!l2_node) {
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+ ret = -ENODEV;
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+ goto out_l2;
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+ }
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+
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+ saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
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+ if (!saw_node) {
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+ ret = -ENODEV;
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+ goto out_saw;
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+ }
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+
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+ reg = of_iomap(acc_node, 0);
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+ if (!reg) {
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+ ret = -ENOMEM;
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+ goto out_map;
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+ }
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+
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+ l2_saw_base = of_iomap(saw_node, 0);
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+ if (!l2_saw_base) {
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+ ret = -ENOMEM;
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+ goto out_saw_map;
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+ }
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+
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+ /* Turn on the BHS, turn off LDO Bypass and power down LDO */
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+ reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
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+ writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
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+ mb();
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+ /* wait for the BHS to settle */
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+ udelay(1);
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+
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+ /* Turn on BHS segments */
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+ reg_val |= 0x3f << BHS_SEG_SHIFT;
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+ writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
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+ mb();
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+ /* wait for the BHS to settle */
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+ udelay(1);
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+
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+ /* Finally turn on the bypass so that BHS supplies power */
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+ reg_val |= 0x3f << LDO_BYP_SHIFT;
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+ writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
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+
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+ /* enable max phases */
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+ writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
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+ mb();
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+ udelay(50);
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+
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+ reg_val = COREPOR_RST | CLAMP;
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+ writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+ udelay(2);
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+
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+ reg_val &= ~CLAMP;
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+ writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+ udelay(2);
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+
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+ reg_val &= ~COREPOR_RST;
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+ writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+
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+ reg_val |= CORE_PWRD_UP;
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+ writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+
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+ ret = 0;
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+
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+ iounmap(l2_saw_base);
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+out_saw_map:
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+ iounmap(reg);
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+out_map:
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+ of_node_put(saw_node);
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+out_saw:
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+ of_node_put(l2_node);
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+out_l2:
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+ of_node_put(acc_node);
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+out_acc:
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+ of_node_put(cpu_node);
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+
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+ return ret;
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+}
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+
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static DEFINE_PER_CPU(int, cold_boot_done);
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static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
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@@ -204,6 +312,11 @@ static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
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return qcom_boot_secondary(cpu, kpssv1_release_secondary);
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}
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+static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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+{
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+ return qcom_boot_secondary(cpu, kpssv2_release_secondary);
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+}
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+
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static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu, map;
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@@ -253,3 +366,13 @@ static struct smp_operations qcom_smp_kpssv1_ops __initdata = {
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#endif
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};
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CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
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+
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+static struct smp_operations qcom_smp_kpssv2_ops __initdata = {
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+ .smp_prepare_cpus = qcom_smp_prepare_cpus,
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+ .smp_secondary_init = qcom_secondary_init,
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+ .smp_boot_secondary = kpssv2_boot_secondary,
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+#ifdef CONFIG_HOTPLUG_CPU
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+ .cpu_die = qcom_cpu_die,
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+#endif
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+};
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+CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);
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--
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1.7.10.4
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