62 lines
1.7 KiB
Diff
62 lines
1.7 KiB
Diff
From 4f43ab43125a12dbc23e352ac0eb4fd80a876fb5 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Fri, 20 Sep 2013 20:29:17 -0300
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Subject: [PATCH] clk: sunxi: Implement MMC phase control
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
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1 file changed, 35 insertions(+)
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index 625089b..6d3286a 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -361,6 +361,41 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
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/**
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+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
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+ */
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+
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+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
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+{
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+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
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+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
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+
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+ struct clk_composite *composite = to_clk_composite(hw);
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+ struct clk_hw *rate_hw = composite->rate_hw;
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+ struct clk_factors *factors = to_clk_factors(rate_hw);
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+ unsigned long flags = 0;
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+ u32 reg;
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+
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+ if (factors->lock)
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+ spin_lock_irqsave(factors->lock, flags);
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+
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+ reg = readl(factors->reg);
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+
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+ /* set sample clock phase control */
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+ reg &= ~(0x7 << 20);
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+ reg |= ((sample & 0x7) << 20);
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+
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+ /* set output clock phase control */
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+ reg &= ~(0x7 << 8);
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+ reg |= ((output & 0x7) << 8);
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+
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+ writel(reg, factors->reg);
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+
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+ if (factors->lock)
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+ spin_unlock_irqrestore(factors->lock, flags);
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+}
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+
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+
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+/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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--
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1.8.5.1
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