34a422794d
This backports multiple patches from kernel 4.10 which are adding missing support for the A64 and the pine64 board. These are the device tree files, the pinctlk and the clock driver. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
122 lines
3.8 KiB
Diff
122 lines
3.8 KiB
Diff
From 51814827190214986c452a166718bf12d32211c7 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Fri, 11 Nov 2016 17:50:36 +0800
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Subject: pinctrl: sunxi: Make sunxi_pconf_group_set use sunxi_pconf_reg helper
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The sunxi_pconf_reg helper introduced in the last patch gives us the
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chance to rework sunxi_pconf_group_set to have it match the structure
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of sunxi_pconf_(group_)get and make it easier to understand.
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For each config to set, it:
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1. checks if the parameter is supported.
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2. checks if the argument is within limits.
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3. converts argument to the register value.
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4. writes to the register with spinlock held.
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As a result the function now blocks unsupported config parameters,
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instead of silently ignoring them.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/sunxi/pinctrl-sunxi.c | 64 +++++++++++++++++------------------
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1 file changed, 32 insertions(+), 32 deletions(-)
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--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
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+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
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@@ -532,23 +532,27 @@ static int sunxi_pconf_group_set(struct
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct sunxi_pinctrl_group *g = &pctl->groups[group];
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- unsigned long flags;
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unsigned pin = g->pin - pctl->desc->pin_base;
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- u32 val, mask;
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- u16 strength;
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- u8 dlevel;
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int i;
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- spin_lock_irqsave(&pctl->lock, flags);
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-
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for (i = 0; i < num_configs; i++) {
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- switch (pinconf_to_config_param(configs[i])) {
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+ enum pin_config_param param;
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+ unsigned long flags;
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+ u32 offset, shift, mask, reg;
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+ u16 arg, val;
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+ int ret;
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+
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+ param = pinconf_to_config_param(configs[i]);
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+ arg = pinconf_to_config_argument(configs[i]);
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+
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+ ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
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+ if (ret < 0)
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+ return ret;
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+
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+ switch (param) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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- strength = pinconf_to_config_argument(configs[i]);
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- if (strength > 40) {
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- spin_unlock_irqrestore(&pctl->lock, flags);
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+ if (arg < 10 || arg > 40)
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return -EINVAL;
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- }
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/*
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* We convert from mA to what the register expects:
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* 0: 10mA
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@@ -556,37 +560,33 @@ static int sunxi_pconf_group_set(struct
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* 2: 30mA
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* 3: 40mA
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*/
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- dlevel = strength / 10 - 1;
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- val = readl(pctl->membase + sunxi_dlevel_reg(pin));
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- mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
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- writel((val & ~mask)
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- | dlevel << sunxi_dlevel_offset(pin),
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- pctl->membase + sunxi_dlevel_reg(pin));
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+ val = arg / 10 - 1;
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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- val = readl(pctl->membase + sunxi_pull_reg(pin));
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- mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
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- writel((val & ~mask),
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- pctl->membase + sunxi_pull_reg(pin));
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+ val = 0;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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- val = readl(pctl->membase + sunxi_pull_reg(pin));
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- mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
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- writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
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- pctl->membase + sunxi_pull_reg(pin));
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+ if (arg == 0)
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+ return -EINVAL;
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+ val = 1;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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- val = readl(pctl->membase + sunxi_pull_reg(pin));
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- mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
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- writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
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- pctl->membase + sunxi_pull_reg(pin));
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+ if (arg == 0)
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+ return -EINVAL;
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+ val = 2;
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break;
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default:
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- break;
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+ /* sunxi_pconf_reg should catch anything unsupported */
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+ WARN_ON(1);
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+ return -ENOTSUPP;
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}
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- } /* for each config */
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- spin_unlock_irqrestore(&pctl->lock, flags);
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+ spin_lock_irqsave(&pctl->lock, flags);
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+ reg = readl(pctl->membase + offset);
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+ reg &= ~(mask << shift);
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+ writel(reg | val << shift, pctl->membase + offset);
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+ spin_unlock_irqrestore(&pctl->lock, flags);
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+ } /* for each config */
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return 0;
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}
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