57 lines
1.6 KiB
Diff
57 lines
1.6 KiB
Diff
commit 0388a0410d590a6c239c1cfaa7d49bffd4ed1101
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Author: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Wed Sep 18 13:32:59 2013 +0200
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MIPS: BCM47XX: Fix clock detection for BCM5354 with 200MHz clock
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Some BCM5354 SoCs are running at 200MHz, but it is not possible to read
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the clock from a register like it is done on some other SoC in ssb and
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bcma. These devices should have a clkfreq nvram configuration value set
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to 200, read it and set the clock to the correct value.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/5842/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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--- a/arch/mips/bcm47xx/time.c
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+++ b/arch/mips/bcm47xx/time.c
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@@ -27,10 +27,14 @@
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#include <linux/ssb/ssb.h>
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#include <asm/time.h>
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#include <bcm47xx.h>
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+#include <bcm47xx_nvram.h>
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void __init plat_time_init(void)
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{
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unsigned long hz = 0;
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+ u16 chip_id = 0;
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+ char buf[10];
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+ int len;
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/*
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* Use deterministic values for initial counter interrupt
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@@ -43,15 +47,23 @@ void __init plat_time_init(void)
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#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
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+ chip_id = bcm47xx_bus.ssb.chip_id;
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break;
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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case BCM47XX_BUS_TYPE_BCMA:
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hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
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+ chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
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break;
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#endif
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}
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+ if (chip_id == 0x5354) {
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+ len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
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+ if (len >= 0 && !strncmp(buf, "200", 4))
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+ hz = 100000000;
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+ }
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+
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if (!hz)
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hz = 100000000;
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