b50fd8c2b3
Register SPI controllers through device tree. We will wire up the clocks at a later stage. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
107 lines
2 KiB
Text
107 lines
2 KiB
Text
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm6348";
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aliases {
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pflash = &pflash;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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spi0 = &lsspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "brcm,bmips3300", "mips,mips4Kc";
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device_type = "cpu";
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reg = <0>;
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};
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};
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cpu_intc: interrupt-controller {
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#address-cells = <0>;
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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memory { device_type = "memory"; reg = <0 0>; };
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pflash: nor@1fc00000 {
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compatible = "cfi-flash";
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reg = <0x1fc00000 0x400000>;
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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ubus@fff00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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interrupt-parent = <&periph_intc>;
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periph_intc: interrupt-controller@fffe000c {
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compatible = "brcm,bcm6345-l1-intc";
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reg = <0xfffe000c 0x8>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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};
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ext_intc: interrupt-controller@fffe0014 {
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compatible = "brcm,bcm6345-ext-intc";
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reg = <0xfffe0014 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <3>, <4>, <5>, <6>;
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brcm,field-width = <5>;
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};
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gpio1: gpio-controller@fffe0400 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0xfffe0400 4>, <0xfffe0408 4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <5>;
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interrupt-parent = <&ext_intc>;
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interrupts = <0 0>, <1 0>, <2 0>, <3 0>;
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interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3";
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};
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gpio0: gpio-controller@fffe0404 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0xfffe0404 4>, <0xfffe040c 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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lsspi: spi@fffe0c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm6348-spi";
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reg = <0xfffe0c00 0x40>;
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interrupts = <1>;
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/* clocks = <&clkctl 9>; */
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};
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};
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};
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