36a96a4493
In current state there's huge regression on ipq806x target that causes the device to transmit broken/malformed frames that are not corrected/detected by error control mechanisms and other less severe issues. https://bugs.lede-project.org/index.php?do=details&task_id=1197 This finally had been narrowed down to patch 0071-pcie-qcom-fixes.patch Meanwhile QSDK contains a handful of commits that add support for ipq806x to upstream qcom pcie driver https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/log/drivers/pci/host/pcie-qcom.c?h=eggplant Unfortunately qca developers do not bother to push it upstream. Using those commits instead of lede 0071 patch fixes mentioned issue and probably many others as it seems that corrupted data has been originating within pcie misconfiguration. Fixes: FS#1197 and probably others Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
113 lines
4 KiB
Diff
113 lines
4 KiB
Diff
From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001
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From: Sham Muthayyan <smuthayy@codeaurora.org>
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Date: Tue, 26 Jul 2016 12:28:31 +0530
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Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x
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Resolved PCIE EP detection errors caused due to missing iATU programming.
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Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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---
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drivers/pci/host/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 77 insertions(+)
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--- a/drivers/pci/host/pcie-qcom.c
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+++ b/drivers/pci/host/pcie-qcom.c
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@@ -52,6 +52,29 @@
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#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
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#define PCIE20_CAP 0x70
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+#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
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+
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+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
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+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
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+
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+#define PCIE20_PLR_IATU_VIEWPORT 0x900
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+#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
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+#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
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+
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+#define PCIE20_PLR_IATU_CTRL1 0x904
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+#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
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+#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
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+
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+#define PCIE20_PLR_IATU_CTRL2 0x908
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+#define PCIE20_PLR_IATU_ENABLE BIT(31)
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+
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+#define PCIE20_PLR_IATU_LBAR 0x90C
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+#define PCIE20_PLR_IATU_UBAR 0x910
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+#define PCIE20_PLR_IATU_LAR 0x914
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+#define PCIE20_PLR_IATU_LTAR 0x918
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+#define PCIE20_PLR_IATU_UTAR 0x91c
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+
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+#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
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#define PERST_DELAY_US 1000
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/* PARF registers */
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@@ -163,6 +186,57 @@ static int qcom_pcie_establish_link(stru
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return dw_pcie_wait_for_link(&pcie->pp);
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}
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+static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
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+{
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+ struct pcie_port *pp = &pcie->pp;
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+
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+ /*
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+ * program and enable address translation region 0 (device config
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+ * address space); region type config;
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+ * axi config address range to device config address range
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+ */
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+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
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+ PCIE20_PLR_IATU_REGION_INDEX(0),
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+ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
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+
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+ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
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+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
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+ writel(pp->cfg0_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
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+ writel((pp->cfg0_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
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+ writel((pp->cfg0_base + pp->cfg0_size - 1),
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+ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
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+ writel(busdev, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
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+ writel(0, pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
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+}
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+
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+static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
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+{
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+ struct pcie_port *pp = &pcie->pp;
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+
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+ /*
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+ * program and enable address translation region 2 (device resource
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+ * address space); region type memory;
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+ * axi device bar address range to device bar address range
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+ */
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+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
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+ PCIE20_PLR_IATU_REGION_INDEX(2),
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+ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
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+
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+ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
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+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
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+ writel(pp->mem_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
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+ writel((pp->mem_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
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+ writel(pp->mem_base + pp->mem_size - 1,
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+ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
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+ writel(pp->mem_bus_addr, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
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+ writel(upper_32_bits(pp->mem_bus_addr),
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+ pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
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+
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+ /* 256B PCIE buffer setting */
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+ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
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+ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
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+}
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+
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static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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@@ -404,6 +478,9 @@ static int qcom_pcie_init_v0(struct qcom
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/* wait for clock acquisition */
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usleep_range(1000, 1500);
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+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
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+ qcom_pcie_prog_viewport_mem2_outbound(pcie);
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+
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return 0;
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err_deassert_ahb:
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