121 lines
3.5 KiB
Diff
121 lines
3.5 KiB
Diff
--- a/drivers/net/ethernet/lantiq_etop.c
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+++ b/drivers/net/ethernet/lantiq_etop.c
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@@ -47,7 +47,7 @@
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#include <xway_dma.h>
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#include <lantiq_platform.h>
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-#define LTQ_ETOP_MDIO 0x11804
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+#define LTQ_ETOP_MDIO_ACC 0x11804
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#define MDIO_REQUEST 0x80000000
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#define MDIO_READ 0x40000000
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#define MDIO_ADDR_MASK 0x1f
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@@ -56,27 +56,38 @@
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#define MDIO_REG_OFFSET 0x10
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#define MDIO_VAL_MASK 0xffff
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-#define PPE32_CGEN 0x800
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-#define LQ_PPE32_ENET_MAC_CFG 0x1840
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+#define LTQ_ETOP_MDIO_CFG 0x11800
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+#define MDIO_CFG_MASK 0x6
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+
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+#define LTQ_ETOP_CFG 0x11808
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+#define LTQ_ETOP_IGPLEN 0x11820
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+#define LTQ_ETOP_MAC_CFG 0x11840
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#define LTQ_ETOP_ENETS0 0x11850
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#define LTQ_ETOP_MAC_DA0 0x1186C
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#define LTQ_ETOP_MAC_DA1 0x11870
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-#define LTQ_ETOP_CFG 0x16020
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-#define LTQ_ETOP_IGPLEN 0x16080
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+
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+#define MAC_CFG_MASK 0xfff
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+#define MAC_CFG_CGEN (1 << 11)
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+#define MAC_CFG_DUPLEX (1 << 2)
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+#define MAC_CFG_SPEED (1 << 1)
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+#define MAC_CFG_LINK (1 << 0)
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#define MAX_DMA_CHAN 0x8
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#define MAX_DMA_CRC_LEN 0x4
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#define MAX_DMA_DATA_LEN 0x600
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#define ETOP_FTCU BIT(28)
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-#define ETOP_MII_MASK 0xf
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-#define ETOP_MII_NORMAL 0xd
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-#define ETOP_MII_REVERSE 0xe
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#define ETOP_PLEN_UNDER 0x40
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-#define ETOP_CGEN 0x800
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#define ETOP_CFG_MII0 0x01
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+#define ETOP_CFG_MASK 0xfff
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+#define ETOP_CFG_FEN0 (1 << 8)
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+#define ETOP_CFG_SEN0 (1 << 6)
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+#define ETOP_CFG_OFF1 (1 << 3)
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+#define ETOP_CFG_REMII0 (1 << 1)
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+#define ETOP_CFG_OFF0 (1 << 0)
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+
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#define LTQ_GBIT_MDIO_CTL 0xCC
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#define LTQ_GBIT_MDIO_DATA 0xd0
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#define LTQ_GBIT_GCTL0 0x68
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@@ -355,16 +366,19 @@ ltq_etop_hw_init(struct net_device *dev)
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/* force the etops link to the gbit to MII */
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mii_mode = PHY_INTERFACE_MODE_MII;
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}
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+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
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+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
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+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
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switch (mii_mode) {
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case PHY_INTERFACE_MODE_RMII:
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- ltq_etop_w32_mask(ETOP_MII_MASK,
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- ETOP_MII_REVERSE, LTQ_ETOP_CFG);
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+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
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+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
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break;
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case PHY_INTERFACE_MODE_MII:
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- ltq_etop_w32_mask(ETOP_MII_MASK,
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- ETOP_MII_NORMAL, LTQ_ETOP_CFG);
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+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
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+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
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break;
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default:
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@@ -385,9 +399,6 @@ ltq_etop_hw_init(struct net_device *dev)
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return -ENOTSUPP;
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}
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- /* enable crc generation */
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- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
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-
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return 0;
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}
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@@ -521,9 +532,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
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((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
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phy_data;
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- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
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+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
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;
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- ltq_etop_w32(val, LTQ_ETOP_MDIO);
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+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
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return 0;
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}
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@@ -534,12 +545,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
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((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
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((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
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- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
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+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
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;
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- ltq_etop_w32(val, LTQ_ETOP_MDIO);
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- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
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+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
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+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
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;
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- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
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+ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
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return val;
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}
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