287 lines
8.1 KiB
Diff
287 lines
8.1 KiB
Diff
From 1387d4f0ebf4b48c09f2ea0d27a02936c3fa0010 Mon Sep 17 00:00:00 2001
|
|
From: John Crispin <blogic@openwrt.org>
|
|
Date: Thu, 31 Mar 2016 02:26:37 +0200
|
|
Subject: [PATCH 054/102] clk: mediatek: Export CPU mux clocks for CPU
|
|
frequency control
|
|
|
|
This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
|
|
for intermediate clock source switching.
|
|
|
|
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
|
---
|
|
drivers/clk/mediatek/Makefile | 2 +-
|
|
drivers/clk/mediatek/clk-cpumux.c | 127 ++++++++++++++++++++++++++++++++
|
|
drivers/clk/mediatek/clk-cpumux.h | 22 ++++++
|
|
drivers/clk/mediatek/clk-mt2701.c | 8 ++
|
|
drivers/clk/mediatek/clk-mt8173.c | 23 ++++++
|
|
include/dt-bindings/clock/mt2701-clk.h | 3 +-
|
|
include/dt-bindings/clock/mt8173-clk.h | 4 +-
|
|
7 files changed, 186 insertions(+), 3 deletions(-)
|
|
create mode 100644 drivers/clk/mediatek/clk-cpumux.c
|
|
create mode 100644 drivers/clk/mediatek/clk-cpumux.h
|
|
|
|
--- a/drivers/clk/mediatek/Makefile
|
|
+++ b/drivers/clk/mediatek/Makefile
|
|
@@ -1,4 +1,4 @@
|
|
-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
|
|
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
|
|
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
|
|
obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
|
|
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
|
|
--- /dev/null
|
|
+++ b/drivers/clk/mediatek/clk-cpumux.c
|
|
@@ -0,0 +1,127 @@
|
|
+/*
|
|
+ * Copyright (c) 2015 Linaro Ltd.
|
|
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License version 2 as
|
|
+ * published by the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ */
|
|
+
|
|
+#include <linux/clk-provider.h>
|
|
+#include <linux/mfd/syscon.h>
|
|
+#include <linux/slab.h>
|
|
+
|
|
+#include "clk-mtk.h"
|
|
+#include "clk-cpumux.h"
|
|
+
|
|
+struct mtk_clk_cpumux {
|
|
+ struct clk_hw hw;
|
|
+ struct regmap *regmap;
|
|
+ u32 reg;
|
|
+ u32 mask;
|
|
+ u8 shift;
|
|
+};
|
|
+
|
|
+static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
|
|
+{
|
|
+ return container_of(_hw, struct mtk_clk_cpumux, hw);
|
|
+}
|
|
+
|
|
+static u8 clk_cpumux_get_parent(struct clk_hw *hw)
|
|
+{
|
|
+ struct mtk_clk_cpumux *mux = to_clk_mux(hw);
|
|
+ int num_parents = clk_hw_get_num_parents(hw);
|
|
+ unsigned int val;
|
|
+
|
|
+ regmap_read(mux->regmap, mux->reg, &val);
|
|
+
|
|
+ val >>= mux->shift;
|
|
+ val &= mux->mask;
|
|
+
|
|
+ if (val >= num_parents)
|
|
+ return -EINVAL;
|
|
+
|
|
+ return val;
|
|
+}
|
|
+
|
|
+static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
|
|
+{
|
|
+ struct mtk_clk_cpumux *mux = to_clk_mux(hw);
|
|
+ u32 mask, val;
|
|
+
|
|
+ val = index << mux->shift;
|
|
+ mask = mux->mask << mux->shift;
|
|
+
|
|
+ return regmap_update_bits(mux->regmap, mux->reg, mask, val);
|
|
+}
|
|
+
|
|
+static const struct clk_ops clk_cpumux_ops = {
|
|
+ .get_parent = clk_cpumux_get_parent,
|
|
+ .set_parent = clk_cpumux_set_parent,
|
|
+};
|
|
+
|
|
+static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
|
|
+ struct regmap *regmap)
|
|
+{
|
|
+ struct mtk_clk_cpumux *cpumux;
|
|
+ struct clk *clk;
|
|
+ struct clk_init_data init;
|
|
+
|
|
+ cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
|
|
+ if (!cpumux)
|
|
+ return ERR_PTR(-ENOMEM);
|
|
+
|
|
+ init.name = mux->name;
|
|
+ init.ops = &clk_cpumux_ops;
|
|
+ init.parent_names = mux->parent_names;
|
|
+ init.num_parents = mux->num_parents;
|
|
+ init.flags = mux->flags;
|
|
+
|
|
+ cpumux->reg = mux->mux_reg;
|
|
+ cpumux->shift = mux->mux_shift;
|
|
+ cpumux->mask = BIT(mux->mux_width) - 1;
|
|
+ cpumux->regmap = regmap;
|
|
+ cpumux->hw.init = &init;
|
|
+
|
|
+ clk = clk_register(NULL, &cpumux->hw);
|
|
+ if (IS_ERR(clk))
|
|
+ kfree(cpumux);
|
|
+
|
|
+ return clk;
|
|
+}
|
|
+
|
|
+int __init mtk_clk_register_cpumuxes(struct device_node *node,
|
|
+ const struct mtk_composite *clks, int num,
|
|
+ struct clk_onecell_data *clk_data)
|
|
+{
|
|
+ int i;
|
|
+ struct clk *clk;
|
|
+ struct regmap *regmap;
|
|
+
|
|
+ regmap = syscon_node_to_regmap(node);
|
|
+ if (IS_ERR(regmap)) {
|
|
+ pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
|
|
+ PTR_ERR(regmap));
|
|
+ return PTR_ERR(regmap);
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < num; i++) {
|
|
+ const struct mtk_composite *mux = &clks[i];
|
|
+
|
|
+ clk = mtk_clk_register_cpumux(mux, regmap);
|
|
+ if (IS_ERR(clk)) {
|
|
+ pr_err("Failed to register clk %s: %ld\n",
|
|
+ mux->name, PTR_ERR(clk));
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ clk_data->clks[mux->id] = clk;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/drivers/clk/mediatek/clk-cpumux.h
|
|
@@ -0,0 +1,22 @@
|
|
+/*
|
|
+ * Copyright (c) 2015 Linaro Ltd.
|
|
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License version 2 as
|
|
+ * published by the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ */
|
|
+
|
|
+#ifndef __DRV_CLK_CPUMUX_H
|
|
+#define __DRV_CLK_CPUMUX_H
|
|
+
|
|
+int mtk_clk_register_cpumuxes(struct device_node *node,
|
|
+ const struct mtk_composite *clks, int num,
|
|
+ struct clk_onecell_data *clk_data);
|
|
+
|
|
+#endif /* __DRV_CLK_CPUMUX_H */
|
|
--- a/drivers/clk/mediatek/clk-mt2701.c
|
|
+++ b/drivers/clk/mediatek/clk-mt2701.c
|
|
@@ -18,6 +18,7 @@
|
|
|
|
#include "clk-mtk.h"
|
|
#include "clk-gate.h"
|
|
+#include "clk-cpumux.h"
|
|
|
|
#include <dt-bindings/clock/mt2701-clk.h>
|
|
|
|
@@ -465,6 +466,10 @@ static const char * const cpu_parents[]
|
|
"mmpll"
|
|
};
|
|
|
|
+static const struct mtk_composite cpu_muxes[] __initconst = {
|
|
+ MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
|
|
+};
|
|
+
|
|
static const struct mtk_composite top_muxes[] __initconst = {
|
|
MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
|
|
0x0040, 0, 3, INVALID_MUX_GATE_BIT),
|
|
@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(str
|
|
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
|
|
clk_data);
|
|
|
|
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
|
|
+ clk_data);
|
|
+
|
|
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
|
if (r)
|
|
pr_err("%s(): could not register clock provider: %d\n",
|
|
--- a/drivers/clk/mediatek/clk-mt8173.c
|
|
+++ b/drivers/clk/mediatek/clk-mt8173.c
|
|
@@ -18,6 +18,7 @@
|
|
|
|
#include "clk-mtk.h"
|
|
#include "clk-gate.h"
|
|
+#include "clk-cpumux.h"
|
|
|
|
#include <dt-bindings/clock/mt8173-clk.h>
|
|
|
|
@@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_pare
|
|
"apll2_div5"
|
|
};
|
|
|
|
+static const char * const ca53_parents[] __initconst = {
|
|
+ "clk26m",
|
|
+ "armca7pll",
|
|
+ "mainpll",
|
|
+ "univpll"
|
|
+};
|
|
+
|
|
+static const char * const ca57_parents[] __initconst = {
|
|
+ "clk26m",
|
|
+ "armca15pll",
|
|
+ "mainpll",
|
|
+ "univpll"
|
|
+};
|
|
+
|
|
+static const struct mtk_composite cpu_muxes[] __initconst = {
|
|
+ MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
|
|
+ MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
|
|
+};
|
|
+
|
|
static const struct mtk_composite top_muxes[] __initconst = {
|
|
/* CLK_CFG_0 */
|
|
MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
|
|
@@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(str
|
|
clk_data);
|
|
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
|
|
|
|
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
|
|
+ clk_data);
|
|
+
|
|
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
|
if (r)
|
|
pr_err("%s(): could not register clock provider: %d\n",
|
|
--- a/include/dt-bindings/clock/mt2701-clk.h
|
|
+++ b/include/dt-bindings/clock/mt2701-clk.h
|
|
@@ -217,7 +217,8 @@
|
|
#define CLK_INFRA_PMICWRAP 17
|
|
#define CLK_INFRA_DDCCI 18
|
|
#define CLK_INFRA_CLK_13M 19
|
|
-#define CLK_INFRA_NR 20
|
|
+#define CLK_INFRA_CPUSEL 20
|
|
+#define CLK_INFRA_NR 21
|
|
|
|
/* PERICFG */
|
|
|
|
--- a/include/dt-bindings/clock/mt8173-clk.h
|
|
+++ b/include/dt-bindings/clock/mt8173-clk.h
|
|
@@ -192,7 +192,9 @@
|
|
#define CLK_INFRA_PMICSPI 10
|
|
#define CLK_INFRA_PMICWRAP 11
|
|
#define CLK_INFRA_CLK_13M 12
|
|
-#define CLK_INFRA_NR_CLK 13
|
|
+#define CLK_INFRA_CA53SEL 13
|
|
+#define CLK_INFRA_CA57SEL 14
|
|
+#define CLK_INFRA_NR_CLK 15
|
|
|
|
/* PERI_SYS */
|
|
|