190 lines
4.3 KiB
Diff
190 lines
4.3 KiB
Diff
--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
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imx6dl-sabresd.dtb \
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imx6dl-wandboard.dtb \
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imx6q-arm2.dtb \
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+ imx6q-gw5400-a.dtb \
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imx6q-sabreauto.dtb \
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imx6q-sabrelite.dtb \
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imx6q-sabresd.dtb \
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--- a/arch/arm/boot/dts/imx6q.dtsi
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+++ b/arch/arm/boot/dts/imx6q.dtsi
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@@ -94,6 +94,14 @@
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MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
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>;
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};
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+
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+ pinctrl_audmux_3: audmux-3 {
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+ fsl,pins = <
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+ MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
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+ MX6Q_PAD_EIM_D25__AUD5_RXC 0x80000000
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+ MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
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+ >;
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+ };
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};
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ecspi1 {
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@@ -201,6 +209,12 @@
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MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
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>;
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};
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+ pinctrl_i2c2_2: i2c2grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
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+ MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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+ >;
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+ };
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};
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i2c3 {
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@@ -210,6 +224,12 @@
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MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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>;
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};
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+ pinctrl_i2c3_2: i2c3grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
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+ MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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+ >;
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+ };
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};
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uart1 {
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@@ -219,6 +239,12 @@
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MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
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>;
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};
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+ pinctrl_uart1_2: uart1grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
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+ MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
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+ >;
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+ };
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};
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uart2 {
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@@ -228,6 +254,21 @@
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MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
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>;
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};
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+ pinctrl_uart2_2: uart2grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
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+ MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
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+ >;
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+ };
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+ };
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+
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+ uart3 {
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+ pinctrl_uart3_1: uart3grp-1 {
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+ fsl,pins = <
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+ MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
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+ MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
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+ >;
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+ };
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};
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uart4 {
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@@ -238,6 +279,15 @@
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>;
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};
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};
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+
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+ uart5 {
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+ pinctrl_uart5_1: uart5grp-1 {
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+ fsl,pins = <
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+ MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
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+ MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
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+ >;
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+ };
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+ };
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usbotg {
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pinctrl_usbotg_1: usbotggrp-1 {
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--- a/arch/arm/mach-imx/mach-imx6q.c
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+++ b/arch/arm/mach-imx/mach-imx6q.c
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@@ -25,6 +25,7 @@
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/opp.h>
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+#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/micrel_phy.h>
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@@ -145,6 +146,65 @@ static void __init imx6q_sabrelite_init(
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imx6q_sabrelite_cko1_setup();
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}
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+/*
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+ * fixup for PEX 8909 bridge to configure GPIO1-7 as output High
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+ * as they are used for slots1-7 PERST#
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+ */
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+static void mx6_ventana_pciesw_early_fixup(struct pci_dev *dev)
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+{
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+ u32 dw;
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+
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+ if (!of_machine_is_compatible("gw,ventana"))
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+ return;
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+
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+ if (dev->devfn != 0)
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+ return;
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+
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+ pci_read_config_dword(dev, 0x62c, &dw);
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+ dw |= 0xaaa8; // GPIO1-7 outputs
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+ pci_write_config_dword(dev, 0x62c, dw);
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+
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+ pci_read_config_dword(dev, 0x644, &dw);
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+ dw |= 0xfe; // GPIO1-7 output high
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+ pci_write_config_dword(dev, 0x644, dw);
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
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+ mx6_ventana_pciesw_early_fixup);
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+
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+/*
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+ * configure PCIe core clock and PCIe ref clock
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+ *
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+ * TODO: disable CLK1 output and use CLK2 input from si52147 as PCIe ref
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+ */
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+static void __init imx6q_ventana_pcie_setup(void)
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+{
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+ struct clk *axi_sel, *axi, *ref;
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+
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+ axi_sel = clk_get_sys(NULL, "pcie_axi_sel");
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+ axi = clk_get_sys(NULL, "axi");
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+ ref = clk_get_sys(NULL, "pcie_ref_125m");
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+ if (IS_ERR(axi_sel) || IS_ERR(axi) || IS_ERR(ref)) {
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+ pr_err("pcie setup failed - can't get clocks\n");
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+ goto put_clk;
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+ }
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+ clk_set_parent(axi_sel, axi);
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+ clk_prepare_enable(ref);
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+
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+put_clk:
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+ if (!IS_ERR(axi_sel))
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+ clk_put(axi_sel);
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+ if (!IS_ERR(axi))
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+ clk_put(axi);
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+ if (!IS_ERR(ref))
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+ clk_put(ref);
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+}
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+
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+static void __init imx6q_ventana_init(void)
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+{
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+ imx6q_ventana_pcie_setup();
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+ imx6q_sabrelite_cko1_setup();
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+}
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+
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static void __init imx6q_1588_init(void)
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{
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struct regmap *gpr;
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@@ -163,6 +223,9 @@ static void __init imx6q_usb_init(void)
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static void __init imx6q_init_machine(void)
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{
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+ if (of_machine_is_compatible("gw,ventana"))
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+ imx6q_ventana_init();
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+
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if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
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imx6q_sabrelite_init();
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