02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
155 lines
3.3 KiB
Diff
155 lines
3.3 KiB
Diff
From 269a71c81438604d27f01ec703daa7f5e3f39e8b Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Sun, 15 Jun 2014 00:48:18 -0500
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Subject: [PATCH 159/182] arm: ipq8064: Add USB3 DT information
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This patch fleshes out the USB3 specific information for the IPQ8064 platform.
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 29 ++++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 90 ++++++++++++++++++++++++++++++
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2 files changed, 119 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -160,5 +160,34 @@
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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};
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+
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+ tcsr@1a400000 {
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+ status = "ok";
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+ qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
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+ };
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+
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+ phy@100f8800 { /* USB3 port 1 HS phy */
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+ status = "ok";
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+ };
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+
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+ phy@100f8830 { /* USB3 port 1 SS phy */
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+ status = "ok";
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+ };
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+
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+ phy@110f8800 { /* USB3 port 0 HS phy */
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+ status = "ok";
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+ };
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+
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+ phy@110f8830 { /* USB3 port 0 SS phy */
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+ status = "ok";
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+ };
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+
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+ usb30@0 {
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+ status = "ok";
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+ };
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+
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+ usb30@1 {
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+ status = "ok";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -4,6 +4,7 @@
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/soc/qcom,tcsr.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -402,5 +403,94 @@
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status = "disabled";
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};
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+
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+ tcsr: tcsr@1a400000 {
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+ compatible = "qcom,tcsr";
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+ reg = <0x1a400000 0x100>;
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+
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+ status = "disabled";
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+ };
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+
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+ hs_phy_1: phy@100f8800 {
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+ compatible = "qcom,dwc3-hsphy";
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+ reg = <0x100f8800 0x30>;
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+ clocks = <&gcc USB30_1_UTMI_CLK>;
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+ clock-names = "utmi";
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+
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+ status = "disabled";
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+ };
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+
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+ ss_phy_1: phy@100f8830 {
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+ compatible = "qcom,dwc3-ssphy";
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+ reg = <0x100f8830 0x30>;
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+
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+ clocks = <&gcc USB30_1_MASTER_CLK>;
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+ clock-names = "ref";
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+
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+ status = "disabled";
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+ };
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+
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+ hs_phy_0: phy@110f8800 {
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+ compatible = "qcom,dwc3-hsphy";
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+ reg = <0x110f8800 0x30>;
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+ clocks = <&gcc USB30_0_UTMI_CLK>;
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+ clock-names = "utmi";
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+
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+ status = "disabled";
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+ };
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+
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+ ss_phy_0: phy@110f8830 {
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+ compatible = "qcom,dwc3-ssphy";
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+ reg = <0x110f8830 0x30>;
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+
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+ clocks = <&gcc USB30_0_MASTER_CLK>;
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+ clock-names = "ref";
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+
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+ status = "disabled";
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+ };
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+
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+ usb3_0: usb30@0 {
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+ compatible = "qcom,dwc3";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc USB30_0_MASTER_CLK>;
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+ clock-names = "core";
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+
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+ ranges;
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+
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+ status = "disabled";
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+
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+ dwc3@11000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x11000000 0xcd00>;
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+ interrupts = <0 110 0x4>;
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+ usb-phy = <&hs_phy_0>, <&ss_phy_0>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ tx-fifo-resize;
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+ dr_mode = "host";
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+ };
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+ };
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+
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+ usb3_1: usb30@1 {
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+ compatible = "qcom,dwc3";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc USB30_1_MASTER_CLK>;
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+ clock-names = "core";
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+
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+ ranges;
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+
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+ status = "disabled";
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+
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+ dwc3@10000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x10000000 0xcd00>;
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+ interrupts = <0 205 0x4>;
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+ usb-phy = <&hs_phy_1>, <&ss_phy_1>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ tx-fifo-resize;
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+ dr_mode = "host";
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+ };
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+ };
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};
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};
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