c4c2a8f00c
The tz and smem reserved-memory information handled in the upstream Linux sources by the SoC specific dtsi and not by the the boards dts. Using the same approach in OpenWrt avoids unneccessary duplication. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
381 lines
7.3 KiB
Text
381 lines
7.3 KiB
Text
/*
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* Device Tree Source for Meraki MR33 (Stinkbug)
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*
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* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
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* Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
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*
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* Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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#include "qcom-ipq4019.dtsi"
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#include "qcom-ipq4019-bus.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/soc/qcom,tcsr.h>
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/ {
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model = "Meraki MR33 Access Point";
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compatible = "meraki,mr33", "qcom,ipq4019";
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aliases {
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led-boot = &status_green;
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led-failsafe = &status_red;
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led-running = &status_green;
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led-upgrade = &power_orange;
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};
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/* Do we really need this defined? */
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>;
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};
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soc {
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mdio@90000 {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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/delete-node/ ethernet-phy@0;
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/delete-node/ ethernet-phy@2;
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/delete-node/ ethernet-phy@3;
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/delete-node/ ethernet-phy@4;
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};
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/* It is a 56-bit counter that supplies the count to the ARM arch
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timers and without upstream driver */
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counter@4a1000 {
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compatible = "qcom,qca-gcnt";
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reg = <0x4a1000 0x4>;
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};
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ess_tcsr@1953000 {
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compatible = "qcom,tcsr";
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reg = <0x1953000 0x1000>;
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qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
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};
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tcsr@1949000 {
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compatible = "qcom,tcsr";
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reg = <0x1949000 0x100>;
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qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
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};
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tcsr@1957000 {
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compatible = "qcom,tcsr";
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reg = <0x1957000 0x100>;
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qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
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};
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serial@78af000 {
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pinctrl-0 = <&serial_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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serial@78b0000 {
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pinctrl-0 = <&serial_1_pins>;
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pinctrl-names = "default";
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status = "okay";
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bluetooth {
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compatible = "ti,cc2650";
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enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
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};
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};
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crypto@8e3a000 {
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status = "okay";
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};
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watchdog@b017000 {
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status = "okay";
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};
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ess-switch@c000000 {
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switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
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switch_lan_bmp = <0x0>; /* lan port bitmap */
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switch_wan_bmp = <0x10>; /* wan port bitmap */
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};
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edma@c080000 {
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qcom,single-phy;
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qcom,num_gmac = <1>;
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phy-mode = "rgmii-rxid";
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status = "okay";
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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power_orange: power {
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label = "mr33:orange:power";
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gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
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panic-indicator;
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};
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};
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};
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&blsp_dma {
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status = "okay";
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};
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&cryptobam {
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status = "okay";
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};
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&gmac0 {
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qcom,phy_mdio_addr = <1>;
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qcom,poll_required = <1>;
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vlan_tag = <0 0x20>;
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};
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&i2c_0 {
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pinctrl-0 = <&i2c_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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at24@50 {
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compatible = "atmel,24c64";
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pagesize = <32>;
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reg = <0x50>;
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read-only; /* This holds our MAC & Meraki board-data */
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};
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};
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&i2c_1 {
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pinctrl-0 = <&i2c_1_pins>;
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pinctrl-names = "default";
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status = "okay";
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lp5562@30 {
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enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
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compatible = "ti,lp5562";
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clock-mode = /bits/8 <2>;
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reg = <0x30>;
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/* RGB led */
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status_red: chan0 {
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chan-name = "mr33:red:status";
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led-cur = /bits/ 8 <0x20>;
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max-cur = /bits/ 8 <0x60>;
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};
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status_green: chan1 {
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chan-name = "mr33:green:status";
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led-cur = /bits/ 8 <0x20>;
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max-cur = /bits/ 8 <0x60>;
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};
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chan2 {
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chan-name = "mr33:blue:status";
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led-cur = /bits/ 8 <0x20>;
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max-cur = /bits/ 8 <0x60>;
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};
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chan3 {
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chan-name = "mr33:white:status";
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led-cur = /bits/ 8 <0x20>;
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max-cur = /bits/ 8 <0x60>;
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};
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};
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};
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&nand {
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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status = "okay";
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nand@0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "sbl1";
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reg = <0x000000000000 0x000000100000>;
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read-only;
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};
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partition@1 {
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label = "mibib";
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reg = <0x000000100000 0x000000100000>;
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read-only;
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};
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partition@2 {
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label = "bootconfig";
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reg = <0x000000200000 0x000000100000>;
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read-only;
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};
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partition@3 {
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label = "qsee";
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reg = <0x000000300000 0x000000100000>;
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read-only;
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};
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partition@4 {
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label = "qsee_alt";
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reg = <0x000000400000 0x000000100000>;
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read-only;
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};
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partition@5 {
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label = "cdt";
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reg = <0x000000500000 0x000000080000>;
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read-only;
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};
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partition@6 {
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label = "cdt_alt";
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reg = <0x000000580000 0x000000080000>;
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read-only;
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};
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partition@7 {
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label = "ddrparams";
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reg = <0x000000600000 0x000000080000>;
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read-only;
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};
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partition@8 {
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label = "u-boot";
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reg = <0x000000700000 0x000000200000>;
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read-only;
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};
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partition@9 {
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label = "u-boot-backup";
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reg = <0x000000900000 0x000000200000>;
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read-only;
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};
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partition@10 {
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label = "ART";
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reg = <0x000000b00000 0x000000080000>;
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read-only;
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};
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partition@11 {
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label = "ubi";
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reg = <0x000000c00000 0x000007000000>;
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};
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};
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};
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};
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&pcie0 {
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status = "okay";
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perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
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wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
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};
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&qpic_bam {
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status = "okay";
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};
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&tlmm {
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/*
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* GPIO43 should be 0/1 whenever the unit is
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* powered through PoE or AC-Adapter.
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* That said, playing with this seems to
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* reset the AP.
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*/
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mdio_pins: mdio_pinmux {
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mux_1 {
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pins = "gpio6";
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function = "mdio";
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bias-pull-up;
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};
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mux_2 {
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pins = "gpio7";
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function = "mdc";
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bias-pull-up;
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};
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};
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serial_0_pins: serial_pinmux {
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mux {
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pins = "gpio16", "gpio17";
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function = "blsp_uart0";
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bias-disable;
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};
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};
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serial_1_pins: serial1_pinmux {
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mux {
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/* We use the i2c-0 pins for serial_1 */
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pins = "gpio8", "gpio9";
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function = "blsp_uart1";
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bias-disable;
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};
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};
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i2c_0_pins: i2c_0_pinmux {
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pinmux {
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function = "blsp_i2c0";
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pins = "gpio20", "gpio21";
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};
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pinconf {
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pins = "gpio20", "gpio21";
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drive-strength = <16>;
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bias-disable;
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};
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};
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i2c_1_pins: i2c_1_pinmux {
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pinmux {
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function = "blsp_i2c1";
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pins = "gpio34", "gpio35";
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};
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pinconf {
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pins = "gpio34", "gpio35";
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drive-strength = <16>;
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bias-disable;
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};
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};
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nand_pins: nand_pins {
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/*
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* There are 18 pins. 15 pins are common between LCD and NAND.
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* The QPIC controller arbitrates between LCD and NAND. Of the
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* remaining 4, 2 are for NAND and 2 are for LCD exclusively.
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*
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* The meraki source hints that the bluetooth module claims
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* pin 52 as well. But sadly, there's no data whenever this
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* is a NAND or LCD exclusive pin or not.
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*/
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pullups {
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pins = "gpio52", "gpio53", "gpio58",
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"gpio59";
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function = "qpic";
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bias-pull-up;
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};
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pulldowns {
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pins = "gpio54", "gpio55", "gpio56",
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"gpio57", "gpio60", "gpio61",
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"gpio62", "gpio63", "gpio64",
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"gpio65", "gpio66", "gpio67",
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"gpio68", "gpio69";
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function = "qpic";
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bias-pull-down;
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};
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};
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};
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&wifi0 {
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status = "okay";
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/* qcom,ath10k-calibration-variant = "MERAKI-MR33"; */
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};
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&wifi1 {
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status = "okay";
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/* qcom,ath10k-calibration-variant = "MERAKI-MR33"; */
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};
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