44 lines
1.7 KiB
Diff
44 lines
1.7 KiB
Diff
From 39ce22c870f4503bed5e451acfcab21eba3b6239 Mon Sep 17 00:00:00 2001
|
|
From: John Crispin <blogic@openwrt.org>
|
|
Date: Sun, 27 Jul 2014 09:49:07 +0100
|
|
Subject: [PATCH 10/53] arch: mips: ralink: add spi1 clocks
|
|
|
|
based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
|
|
|
|
Signed-off-by: John Crispin <blogic@openwrt.org>
|
|
---
|
|
arch/mips/ralink/mt7620.c | 1 +
|
|
arch/mips/ralink/rt305x.c | 1 +
|
|
arch/mips/ralink/rt3883.c | 1 +
|
|
3 files changed, 3 insertions(+)
|
|
|
|
--- a/arch/mips/ralink/mt7620.c
|
|
+++ b/arch/mips/ralink/mt7620.c
|
|
@@ -436,6 +436,7 @@ void __init ralink_clk_init(void)
|
|
ralink_clk_add("10000100.timer", periph_rate);
|
|
ralink_clk_add("10000120.watchdog", periph_rate);
|
|
ralink_clk_add("10000b00.spi", sys_rate);
|
|
+ ralink_clk_add("10000b40.spi", sys_rate);
|
|
ralink_clk_add("10000c00.uartlite", periph_rate);
|
|
ralink_clk_add("10180000.wmac", xtal_rate);
|
|
|
|
--- a/arch/mips/ralink/rt305x.c
|
|
+++ b/arch/mips/ralink/rt305x.c
|
|
@@ -201,6 +201,7 @@ void __init ralink_clk_init(void)
|
|
ralink_clk_add("cpu", cpu_rate);
|
|
ralink_clk_add("sys", sys_rate);
|
|
ralink_clk_add("10000b00.spi", sys_rate);
|
|
+ ralink_clk_add("10000b40.spi", sys_rate);
|
|
ralink_clk_add("10000100.timer", wdt_rate);
|
|
ralink_clk_add("10000120.watchdog", wdt_rate);
|
|
ralink_clk_add("10000500.uart", uart_rate);
|
|
--- a/arch/mips/ralink/rt3883.c
|
|
+++ b/arch/mips/ralink/rt3883.c
|
|
@@ -109,6 +109,7 @@ void __init ralink_clk_init(void)
|
|
ralink_clk_add("10000120.watchdog", sys_rate);
|
|
ralink_clk_add("10000500.uart", 40000000);
|
|
ralink_clk_add("10000b00.spi", sys_rate);
|
|
+ ralink_clk_add("10000b40.spi", sys_rate);
|
|
ralink_clk_add("10000c00.uartlite", 40000000);
|
|
ralink_clk_add("10100000.ethernet", sys_rate);
|
|
ralink_clk_add("10180000.wmac", 40000000);
|