3af779eb17
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.11, and Linux v3.12. This work mainly covers: * Ground work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family,and the Armada family. * Further updates to the mvebu MBus. * Work and ground work for enabling MSI on the Armada family. * some phy / mdio bus initialization related work. * Device tree binding documentation update. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39565
60 lines
1.8 KiB
Diff
60 lines
1.8 KiB
Diff
From 98e6b600e81f71f8621e316f5d46cf261a9f1da4 Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Mon, 25 Nov 2013 17:26:47 +0100
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Subject: [PATCH 088/203] ARM: mvebu: re-enable PCIe on Armada 370 DB
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Commit 14fd8ed0a7fd19913 ("ARM: mvebu: Relocate Armada 370/XP PCIe
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device tree nodes") relocated the PCIe controller DT nodes one level
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up in the Device Tree, to reflect a more correct representation of the
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hardware introduced by the mvebu-mbus Device Tree binding.
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However, while most of the boards were properly adjusted accordingly,
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the Armada 370 DB board was left unchanged, and therefore, PCIe is
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seen as not enabled on this board. This patch fixes that by moving the
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PCIe controller node one level-up in armada-370-db.dts.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Cc: stable@vger.kernel.org
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---
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arch/arm/boot/dts/armada-370-db.dts | 28 ++++++++++++++--------------
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1 file changed, 14 insertions(+), 14 deletions(-)
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--- a/arch/arm/boot/dts/armada-370-db.dts
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+++ b/arch/arm/boot/dts/armada-370-db.dts
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@@ -99,22 +99,22 @@
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spi-max-frequency = <50000000>;
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};
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};
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+ };
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- pcie-controller {
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+ pcie-controller {
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+ status = "okay";
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+ /*
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+ * The two PCIe units are accessible through
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+ * both standard PCIe slots and mini-PCIe
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+ * slots on the board.
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+ */
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+ pcie@1,0 {
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+ /* Port 0, Lane 0 */
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+ status = "okay";
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+ };
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+ pcie@2,0 {
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+ /* Port 1, Lane 0 */
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status = "okay";
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- /*
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- * The two PCIe units are accessible through
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- * both standard PCIe slots and mini-PCIe
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- * slots on the board.
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- */
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- pcie@1,0 {
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- /* Port 0, Lane 0 */
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- status = "okay";
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- };
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- pcie@2,0 {
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- /* Port 1, Lane 0 */
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- status = "okay";
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- };
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};
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};
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};
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