0d9f760f27
Includes memory allocation fixes as well as several networking fixes. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 37103
59 lines
1.5 KiB
Diff
59 lines
1.5 KiB
Diff
From c7150f86dfb0fe2613af3c5bd1c0c587130b9460 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 20 May 2013 20:57:09 +0200
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Subject: [PATCH 133/164] MIPS: ralink: add verbose pmu info
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Print the PMU and LDO settings on boot.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -20,6 +20,22 @@
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#include "common.h"
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+/* analog */
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+#define PMU0_CFG 0x88
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+#define PMU_SW_SET BIT(28)
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+#define A_DCDC_EN BIT(24)
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+#define A_SSC_PERI BIT(19)
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+#define A_SSC_GEN BIT(18)
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+#define A_SSC_M 0x3
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+#define A_SSC_S 16
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+#define A_DLY_M 0x7
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+#define A_DLY_S 8
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+#define A_VTUNE_M 0xff
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+
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+/* digital */
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+#define PMU1_CFG 0x8C
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+#define DIG_SW_SEL BIT(25)
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+
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/* does the board have sdram or ddram */
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static int dram_type;
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@@ -187,6 +203,8 @@ void prom_soc_init(struct ralink_soc_inf
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u32 n1;
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u32 rev;
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u32 cfg0;
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+ u32 pmu0;
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+ u32 pmu1;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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@@ -234,4 +252,12 @@ void prom_soc_init(struct ralink_soc_inf
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BUG();
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}
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soc_info->mem_base = MT7620_DRAM_BASE;
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+
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+ pmu0 = __raw_readl(sysc + PMU0_CFG);
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+ pmu1 = __raw_readl(sysc + PMU1_CFG);
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+
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+ pr_info("Analog PMU set to %s control\n",
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+ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
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+ pr_info("Digital PMU set to %s control\n",
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+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
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}
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