3b88f74bbe
This backports some more patches from kernel 4.11 adding more devices to the device tree of the A64 SoC. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
50 lines
1.5 KiB
Diff
50 lines
1.5 KiB
Diff
From a3e8f4926248b3c12933aacec4432e9b6de004bb Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Mon, 9 Jan 2017 16:39:15 +0100
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Subject: arm64: allwinner: a64: Add MMC pinctrl nodes
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The A64 only has a single set of pins for each MMC controller. Since we
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already have boards that require all of them, let's add them to the DTSI.
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Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
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Acked-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++++++++++++++++++++
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1 file changed, 25 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -243,6 +243,31 @@
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function = "i2c1";
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};
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+ mmc0_pins: mmc0-pins {
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+ pins = "PF0", "PF1", "PF2", "PF3",
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+ "PF4", "PF5";
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+ function = "mmc0";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
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+ mmc1_pins: mmc1-pins {
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+ pins = "PG0", "PG1", "PG2", "PG3",
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+ "PG4", "PG5";
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+ function = "mmc1";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
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+ mmc2_pins: mmc2-pins {
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+ pins = "PC1", "PC5", "PC6", "PC8", "PC9",
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+ "PC10","PC11", "PC12", "PC13",
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+ "PC14", "PC15", "PC16";
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+ function = "mmc2";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
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uart0_pins_a: uart0@0 {
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pins = "PB8", "PB9";
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function = "uart0";
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