b0971e69f2
Thanks to the qi-hardware project - especially to Lars, Maarten and Xiangfu SVN-Revision: 31218
95 lines
3 KiB
Diff
95 lines
3 KiB
Diff
From 2dcb0ca66d0bffc23d5f001fad81fb1a7a2c371b Mon Sep 17 00:00:00 2001
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From: Maarten ter Huurne <maarten@treewalker.org>
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Date: Tue, 28 Jun 2011 22:28:59 +0200
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Subject: [PATCH 14/21] MIPS: JZ4740: reset: Initialize hibernate wakeup
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counters.
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In hibernation mode only the wakeup logic and the RTC are left running,
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so this is what users perceive as power down.
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If the counters are not initialized, the corresponding pin (typically
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connected to the power button) has to be asserted for two seconds
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before the device wakes up. Most users expect a shorter wakeup time.
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I took the timing values of 100 ms and 60 ms from BouKiCHi's patch for
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the Dingoo A320 kernel.
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---
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arch/mips/jz4740/reset.c | 46 ++++++++++++++++++++++++++++++++++++++++------
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1 files changed, 40 insertions(+), 6 deletions(-)
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diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c
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index 5f1fb95..e6d1d7b 100644
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--- a/arch/mips/jz4740/reset.c
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+++ b/arch/mips/jz4740/reset.c
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@@ -21,6 +21,9 @@
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#include <asm/mach-jz4740/base.h>
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#include <asm/mach-jz4740/timer.h>
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+#include "reset.h"
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+#include "clock.h"
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+
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static void jz4740_halt(void)
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{
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while (1) {
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@@ -53,21 +56,52 @@ static void jz4740_restart(char *command)
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jz4740_halt();
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}
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-#define JZ_REG_RTC_CTRL 0x00
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-#define JZ_REG_RTC_HIBERNATE 0x20
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+#define JZ_REG_RTC_CTRL 0x00
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+#define JZ_REG_RTC_HIBERNATE 0x20
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+#define JZ_REG_RTC_WAKEUP_FILTER 0x24
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+#define JZ_REG_RTC_RESET_COUNTER 0x28
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-#define JZ_RTC_CTRL_WRDY BIT(7)
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+#define JZ_RTC_CTRL_WRDY BIT(7)
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+#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
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+#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
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-static void jz4740_power_off(void)
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+static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base)
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{
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- void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
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uint32_t ctrl;
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-
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do {
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ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
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} while (!(ctrl & JZ_RTC_CTRL_WRDY));
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+}
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+static void jz4740_power_off(void)
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+{
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+ void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38);
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+ unsigned long long wakeup_filter_ticks;
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+ unsigned long long reset_counter_ticks;
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+
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+ /* Set minimum wakeup pin assertion time: 100 ms.
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+ Range is 0 to 2 sec if RTC is clocked at 32 kHz. */
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+ wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000;
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+ if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
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+ wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
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+ else
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+ wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
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+ jz4740_rtc_wait_ready(rtc_base);
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+ writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER);
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+
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+ /* Set reset pin low-level assertion time after wakeup: 60 ms.
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+ Range is 0 to 125 ms if RTC is clocked at 32 kHz. */
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+ reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000;
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+ if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
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+ reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
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+ else
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+ reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
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+ jz4740_rtc_wait_ready(rtc_base);
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+ writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER);
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+
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+ jz4740_rtc_wait_ready(rtc_base);
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writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
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+
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jz4740_halt();
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}
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--
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1.7.5.4
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