102c6df148
mtd_speedtest results:
page write speed
old new delta
DB120 209 KiB/s 226 KiB/s +8.13%
TL-WR1043ND v1 122 KiB/s 148 KiB/s +21.31%
TL-WR703N v1 153 KiB/s 194 KiB/s +26.80%
TL-MR3220 v1 130 KiB/s 156 KiB/s +20.00%
TL-WR2543ND v1 158 KiB/s 202 KiB/s +27.85%
TL-WR741ND v2 122 KiB/s 152 KiB/s +24.59%
ALFA AP96 229 KiB/s 260 KiB/s +13.54%
WNDR3700 202 KiB/s 223 KiB/s +10.40%
page read speed
old new delta
DB120 691 KiB/s 929 KiB/s +34.44%
TL-WR1043ND v1 372 KiB/s 754 KiB/s +102.69%
TL-WR703N v1 375 KiB/s 745 KiB/s +98.67%
TL-MR3220 v1 372 KiB/s 752 KiB/s +102.15%
TL-WR2543ND v1 307 KiB/s 564 KiB/s +83.71%
TL-WR741ND v2 315 KiB/s 525 KiB/s +66.67%
ALFA AP96 515 KiB/s 702 KiB/s +36.31%
WNDR3700 515 KiB/s 697 KiB/s +35.34%
SVN-Revision: 31117
122 lines
3.2 KiB
Diff
122 lines
3.2 KiB
Diff
From 8e948c035dd7983eccc3a889f2497e64044f3a31 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Wed, 11 Jan 2012 20:06:35 +0100
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Subject: [PATCH 1/7] spi/ath79: add delay between SCK changes
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The driver uses the "as fast as it can" approach
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to drive the SCK signal. However this does not
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work with certain low speed SPI chips (e.g. the
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PCF2123 RTC chip). Add per-bit slowdowns in order
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to be able to use the driver with such chips as
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well.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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drivers/spi/spi-ath79.c | 44 +++++++++++++++++++++++++++++++++++++++++++-
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1 files changed, 43 insertions(+), 1 deletions(-)
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -24,17 +24,24 @@
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#include <linux/spi/spi_bitbang.h>
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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+#include <linux/clk.h>
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+#include <linux/err.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79_spi_platform.h>
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#define DRV_NAME "ath79-spi"
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+#define ATH79_SPI_RRW_DELAY_FACTOR 12000
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+#define MHZ (1000 * 1000)
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+
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struct ath79_spi {
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struct spi_bitbang bitbang;
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u32 ioc_base;
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u32 reg_ctrl;
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void __iomem *base;
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+ struct clk *clk;
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+ unsigned rrw_delay;
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};
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static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
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@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_sp
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return spi_master_get_devdata(spi->master);
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}
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+static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
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+{
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+ if (nsecs > sp->rrw_delay)
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+ ndelay(nsecs - sp->rrw_delay);
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+}
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+
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static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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@@ -184,7 +197,9 @@ static u32 ath79_spi_txrx_mode0(struct s
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/* setup MSB (to slave) on trailing edge */
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
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+ ath79_spi_delay(sp, nsecs);
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
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+ ath79_spi_delay(sp, nsecs);
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word <<= 1;
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}
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@@ -198,6 +213,7 @@ static __devinit int ath79_spi_probe(str
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struct ath79_spi *sp;
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struct ath79_spi_platform_data *pdata;
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struct resource *r;
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+ unsigned long rate;
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int ret;
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master = spi_alloc_master(&pdev->dev, sizeof(*sp));
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@@ -239,12 +255,36 @@ static __devinit int ath79_spi_probe(str
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goto err_put_master;
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}
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+ sp->clk = clk_get(&pdev->dev, "ahb");
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+ if (IS_ERR(sp->clk)) {
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+ ret = PTR_ERR(sp->clk);
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+ goto err_unmap;
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+ }
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+
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+ ret = clk_enable(sp->clk);
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+ if (ret)
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+ goto err_clk_put;
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+
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+ rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
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+ if (!rate) {
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+ ret = -EINVAL;
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+ goto err_clk_disable;
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+ }
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+
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+ sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
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+ dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
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+ sp->rrw_delay);
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+
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ret = spi_bitbang_start(&sp->bitbang);
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if (ret)
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- goto err_unmap;
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+ goto err_clk_disable;
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return 0;
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+err_clk_disable:
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+ clk_disable(sp->clk);
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+err_clk_put:
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+ clk_put(sp->clk);
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err_unmap:
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iounmap(sp->base);
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err_put_master:
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@@ -259,6 +299,8 @@ static __devexit int ath79_spi_remove(st
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struct ath79_spi *sp = platform_get_drvdata(pdev);
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spi_bitbang_stop(&sp->bitbang);
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+ clk_disable(sp->clk);
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+ clk_put(sp->clk);
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iounmap(sp->base);
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platform_set_drvdata(pdev, NULL);
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spi_master_put(sp->bitbang.master);
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