75 lines
2.5 KiB
Diff
75 lines
2.5 KiB
Diff
From d211df2956ae9d696bb0cab985426e0d236544b8 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Mon, 2 Jul 2012 17:16:00 +0200
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Subject: [PATCH 17/20] ath9k: fix PLL initialization for AR9550
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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---
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drivers/net/wireless/ath/ath9k/hw.c | 27 +++++++++++++++++++--------
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1 files changed, 19 insertions(+), 8 deletions(-)
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -861,7 +861,7 @@ static void ath9k_hw_init_pll(struct ath
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/* program BB PLL phase_shift */
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
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AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
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- } else if (AR_SREV_9340(ah)) {
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+ } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
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u32 regval, pll2_divint, pll2_divfrac, refdiv;
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
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@@ -875,9 +875,15 @@ static void ath9k_hw_init_pll(struct ath
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pll2_divfrac = 0x1eb85;
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refdiv = 3;
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} else {
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- pll2_divint = 88;
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- pll2_divfrac = 0;
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- refdiv = 5;
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+ if (AR_SREV_9340(ah)) {
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+ pll2_divint = 88;
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+ pll2_divfrac = 0;
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+ refdiv = 5;
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+ } else {
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+ pll2_divint = 0x11;
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+ pll2_divfrac = 0x26666;
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+ refdiv = 1;
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+ }
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}
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regval = REG_READ(ah, AR_PHY_PLL_MODE);
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@@ -890,8 +896,12 @@ static void ath9k_hw_init_pll(struct ath
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udelay(100);
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regval = REG_READ(ah, AR_PHY_PLL_MODE);
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- regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
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- (0x4 << 26) | (0x18 << 19);
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+ if (AR_SREV_9340(ah))
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+ regval = (regval & 0x80071fff) | (0x1 << 30) |
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+ (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
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+ else
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+ regval = (regval & 0x80071fff) | (0x3 << 30) |
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+ (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
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REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
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REG_WRITE(ah, AR_PHY_PLL_MODE,
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REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
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@@ -902,7 +912,8 @@ static void ath9k_hw_init_pll(struct ath
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
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- if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
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+ if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
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+ AR_SREV_9550(ah))
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udelay(1000);
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/* Switch the core clock for ar9271 to 117Mhz */
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@@ -915,7 +926,7 @@ static void ath9k_hw_init_pll(struct ath
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REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
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- if (AR_SREV_9340(ah)) {
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+ if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
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if (ah->is_clk_25mhz) {
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REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
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REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
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