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openwrtv3/package/boot/uboot-layerscape/patches/0039-armv8-ls1012a-Add-support-of-ls1012afrdm-board.patch
Yutang Jiang 15a14cf166 layerscape: add 64b/32b target for ls1012ardb device 
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-10-31 17:00:10 +01:00

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From 6aaa5973b9ae8452a546e0666b2389bb163fb949 Mon Sep 17 00:00:00 2001
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Date: Thu, 19 May 2016 16:45:27 +0530
Subject: [PATCH 39/93] armv8: ls1012a: Add support of ls1012afrdm board
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
---
arch/arm/Kconfig | 10 ++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-ls1012a-frdm.dts | 16 +++
arch/arm/dts/fsl-ls1012a-frdm.dtsi | 39 ++++++
board/freescale/ls1012afrdm/Kconfig | 15 +++
board/freescale/ls1012afrdm/MAINTAINERS | 6 +
board/freescale/ls1012afrdm/Makefile | 7 ++
board/freescale/ls1012afrdm/README | 94 +++++++++++++++
board/freescale/ls1012afrdm/ls1012afrdm.c | 183 +++++++++++++++++++++++++++++
configs/ls1012afrdm_qspi_defconfig | 10 ++
include/configs/ls1012afrdm.h | 59 ++++++++++
11 files changed, 441 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
create mode 100644 board/freescale/ls1012afrdm/Kconfig
create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
create mode 100644 board/freescale/ls1012afrdm/Makefile
create mode 100644 board/freescale/ls1012afrdm/README
create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
create mode 100644 configs/ls1012afrdm_qspi_defconfig
create mode 100644 include/configs/ls1012afrdm.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b536684..23fce38 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -669,6 +669,15 @@ config TARGET_LS1012ARDB
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1012AFRDM
+ bool "Support ls1012afrdm"
+ select ARM64
+ help
+ Support for Freescale LS1012AFRDM platform.
+ The LS1012A Freedom board (FRDM) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -816,6 +825,7 @@ source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9e8137b..de023b4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
fsl-ls1012a-qds.dtb \
- fsl-ls1012a-rdb.dtb
+ fsl-ls1012a-rdb.dtb \
+ fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
new file mode 100644
index 0000000..3a06c0a
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
new file mode 100644
index 0000000..9f0db91
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A FREEDOM Board";
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 0000000..a34521c
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+ default "ls1012afrdm"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012afrdm"
+
+endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644
index 0000000..2f31d0f
--- /dev/null
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012afrdm/
+F: include/configs/ls1012afrdm.h
+F: configs/ls1012afrdm_defconfig
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
new file mode 100644
index 0000000..dbfa2ce
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
new file mode 100644
index 0000000..0aadbb1
--- /dev/null
+++ b/board/freescale/ls1012afrdm/README
@@ -0,0 +1,94 @@
+Overview
+--------
+The LS1012AFRDM power supplies (PS) provide all the voltages necessary
+for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
+and other onboard peripherals.
+
+LS1012A SoC Overview
+--------------------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+ 16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+ Two Serdes PLLs supported for usage by any SerDes data lane
+ Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+ - One PCI Express Gen2 controller, supporting x1 operation
+ - One serial ATA (SATA Gen 3.0) controller
+ - One USB 3.0/2.0 controller with integrated PHY
+ - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+ - One quad serial peripheral interface (QuadSPI) controller
+ - One serial peripheral interface (SPI) controller
+ - Two enhanced secure digital host controllers
+ - Two I2C controllers
+ - One 16550 compliant DUART (two UART interfaces)
+ - Two general purpose IOs (GPIO)
+ - Two FlexTimers
+ - Five synchronous audio interfaces (SAI)
+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+ - Single-source clocking solution enabling generation of core, platform,
+ DDR, SerDes, and USB clocks from a single external crystal and internal
+ crystaloscillator
+ - Thermal monitor unit (TMU) with +/- 3C accuracy
+ - Two WatchDog timers
+ - ARM generic timer
+ - QorIQ platform's trust architecture 2.1
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+ - 2 SGMII 1G PHYs
+ - DDR Controller
+ - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ operating at 1.35 V
+ - QSPI
+ - Onboard 512 Mbit QSPI flash memory running at speed up
+ to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+ - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+ Micro-AB connector.
+ - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+ as a Micro-AB device.
+ - I2C controller
+ - One I2C bus with connectivity to Arduino headers
+ - UART
+ - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+ - ARM Cortex® 10-pin JTAG connector for LS1012A
+ - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+ - One SAI port, SAI 2 with full duplex support
+ - Clocks
+ - 25 MHz crystal for LS1012A
+ - 8 MHz Crystal for K20
+ - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+ - 5 V input supply from USB
+ - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+ other board interfaces
+
+Booting Options
+---------------
+a) QSPI Flash 1
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644
index 0000000..6be8951
--- /dev/null
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ puts("Board: LS1012AFRDM ");
+
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ /* Set MMDC_MDSCR[CON_REQ] */
+ out_be32(&mmdc->mdscr, 0x00008000);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, 0x12554000);
+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
+ out_be32(&mmdc->mdcfg1, 0xff328f64);
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, 0x00000680);
+ out_be32(&mmdc->mpmur0, 0x00000800);
+ out_be32(&mmdc->mdrwd, 0x00002000);
+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, 0x00bf1023);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, 0x04180000);
+ out_be32(&mmdc->mdasp, 0x0000007f);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, 0x84180000);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, 0x00088032);
+ out_be32(&mmdc->mdscr, 0x00008033);
+ out_be32(&mmdc->mdscr, 0x00048031);
+ out_be32(&mmdc->mdscr, 0x19308030);
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, 0x04008040);
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, 0x00848031);
+ out_be32(&mmdc->mdscr, 0x00008200);
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, 0x00048031);
+ out_be32(&mmdc->mdscr, 0x00008000);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, 0x04008050);
+ out_be32(&mmdc->mdscr, 0x00048033);
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
+ out_be32(&mmdc->mprddlctl, 0x40404040);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
+
+ out_be32(&mmdc->mdscr, 0x00008033);
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, 0x04008050);
+ out_be32(&mmdc->mdscr, 0x00048033);
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
+
+ out_be32(&mmdc->mdscr, 0x00008033);
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, 0x00030035);
+ out_be32(&mmdc->mapsr, 0x00001067);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, 0x0);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = 0x20000000;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ /* fixup DT for the two DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
new file mode 100644
index 0000000..e27181c
--- /dev/null
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+# CONFIG_CMD_IMLS is not set
+CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
new file mode 100644
index 0000000..3231ab7
--- /dev/null
+++ b/include/configs/ls1012afrdm.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_REALTEK
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_USB_DWC3
+#define CONFIG_USB_DWC3_GADGET
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
+#define CONFIG_USB_GADGET_DUALSPEED
+
+/* USB Gadget ums command */
+#define CONFIG_CMD_USB_MASS_STORAGE
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
--
1.7.9.5
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