15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
67 lines
2.5 KiB
Diff
67 lines
2.5 KiB
Diff
From dec7ec15a9c2f2c3e0a09bb9cda8a24e4d469242 Mon Sep 17 00:00:00 2001
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From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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Date: Fri, 6 May 2016 09:09:32 +0530
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Subject: [PATCH 24/93] config: ls1012aqds: Add USB EHCI support for
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ls1012aqds
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Add USB EHCI support for ls1012aqds platform
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Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
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Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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---
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.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
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include/configs/ls1012aqds.h | 5 +++++
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include/usb/ehci-fsl.h | 2 +-
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3 files changed, 7 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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index 3e37f00..24add1a 100644
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--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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@@ -36,6 +36,7 @@
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#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
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#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
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#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
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+#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
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diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
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index bb433de..51ca902 100644
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--- a/include/configs/ls1012aqds.h
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+++ b/include/configs/ls1012aqds.h
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@@ -109,6 +109,8 @@
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#ifdef CONFIG_HAS_FSL_DR_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_FSL
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+#define CONFIG_USB_ULPI
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+#define CONFIG_USB_ULPI_VIEWPORT
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#endif
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@@ -121,6 +123,9 @@
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#define CONFIG_USB_XHCI_DWC3
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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+#endif
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+
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+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
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#define CONFIG_CMD_USB
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#define CONFIG_USB_STORAGE
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#define CONFIG_CMD_EXT2
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diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
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index b8d78d0..94b1efa 100644
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--- a/include/usb/ehci-fsl.h
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+++ b/include/usb/ehci-fsl.h
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@@ -163,7 +163,7 @@
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#elif defined(CONFIG_MPC512X)
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#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
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#define CONFIG_SYS_FSL_USB2_ADDR 0
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-#elif defined(CONFIG_LS102XA)
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+#elif defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
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#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
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#define CONFIG_SYS_FSL_USB2_ADDR 0
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#endif
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--
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1.7.9.5
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