15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
50 lines
1.7 KiB
Diff
50 lines
1.7 KiB
Diff
From 8aad7c4c5d8becaf6c60e1585c8e70010b3c0ce2 Mon Sep 17 00:00:00 2001
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From: Makarand Pawagi <makarand.pawagi@mindspeed.com>
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Date: Mon, 2 May 2016 09:33:45 +0530
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Subject: [PATCH 19/93] armv8: ls1012a: Add CSU assignment for eSDHC2, SAI1,
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SAI2, SAI3, SAI4
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Access settings for different IPs has to be enabled through CSU registers. Following
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IP's are added for LS1012A:
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Added CSU ID for eSDHC-2, reg: CSL40_REG[23:16]
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Added CSU ID for SAI-1, reg: CSL41_REG[7:0]
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Added CSU ID for SAI-2, reg: CSL41_REG[23:16]
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Added CSU ID for SAI-3, reg: CSL42_REG[7:0]
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Added CSU ID for SAI-4, reg: CSL42_REG[23:16
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---
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.../include/asm/arch-fsl-layerscape/ns_access.h | 10 ++++++++++
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1 file changed, 10 insertions(+)
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diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
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index a3ccdb0..d6642a7 100644
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--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
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+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
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@@ -69,7 +69,12 @@ enum csu_cslx_ind {
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CSU_CSLX_IIC4 = 77,
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CSU_CSLX_WDT4,
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CSU_CSLX_WDT3,
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+ CSU_CSLX_ESDHC2 = 80,
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CSU_CSLX_WDT5 = 81,
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+ CSU_CSLX_SAI2,
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+ CSU_CSLX_SAI1,
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+ CSU_CSLX_SAI4,
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+ CSU_CSLX_SAI3,
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CSU_CSLX_FTM2 = 86,
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CSU_CSLX_FTM1,
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CSU_CSLX_FTM4,
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@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
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{CSU_CSLX_IIC4, CSU_ALL_RW},
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{CSU_CSLX_WDT4, CSU_ALL_RW},
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{CSU_CSLX_WDT3, CSU_ALL_RW},
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+ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
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{CSU_CSLX_WDT5, CSU_ALL_RW},
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+ {CSU_CSLX_SAI2, CSU_ALL_RW},
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+ {CSU_CSLX_SAI1, CSU_ALL_RW},
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+ {CSU_CSLX_SAI4, CSU_ALL_RW},
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+ {CSU_CSLX_SAI3, CSU_ALL_RW},
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{CSU_CSLX_FTM2, CSU_ALL_RW},
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{CSU_CSLX_FTM1, CSU_ALL_RW},
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{CSU_CSLX_FTM4, CSU_ALL_RW},
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--
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1.7.9.5
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