15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
38 lines
1.4 KiB
Diff
38 lines
1.4 KiB
Diff
From 5a5108627b16ab33fb82c16e49ac926ef3a901b8 Mon Sep 17 00:00:00 2001
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From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Date: Wed, 6 Apr 2016 17:44:22 +0530
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Subject: [PATCH 11/93] armv8: fsl-layerscape: fix compile warning "rcw_tmp"
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
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‘get_sys_info’:
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arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
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unused variable ‘rcw_tmp’ [-Wunused-variable]
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u32 rcw_tmp;
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Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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---
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.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 ++++-
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1 file changed, 4 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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index d301fff..078b087 100644
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--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
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struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
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u32 ccr;
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#endif
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-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
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+#if (defined(CONFIG_FSL_ESDHC) &&\
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+ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
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+ defined(CONFIG_SYS_DPAA_FMAN)
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+
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u32 rcw_tmp;
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#endif
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struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
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--
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1.7.9.5
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