15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
82 lines
2.2 KiB
Diff
82 lines
2.2 KiB
Diff
From b3bbf1aeb0245a0f5565f669dd4b2f5f5be40d8a Mon Sep 17 00:00:00 2001
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From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Date: Wed, 16 Mar 2016 08:43:55 +0530
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Subject: [PATCH 08/93] armv8/ls1043a: Add the OCRAM initialization
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Clear the content to zero and the ECC error bit of OCRAM1/2.
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The OCRAM must be initialized to ZERO by the unit of 8-Byte before
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accessing it, or else it will generate ECC error. And the IBR has
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accessed the OCRAM before this initialization, so the ECC error
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status bit should to be cleared.
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Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
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Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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---
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arch/arm/cpu/armv8/start.S | 39 +++++++++++++++++++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
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index dd583c9..235213f 100644
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--- a/arch/arm/cpu/armv8/start.S
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+++ b/arch/arm/cpu/armv8/start.S
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@@ -11,6 +11,9 @@
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#include <asm/macro.h>
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#include <asm/armv8/mmu.h>
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+#define DCSR_SYS_DCFG_SBEESR2 0x20140534
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+#define DCSR_SYS_DCFG_MBEESR2 0x20140544
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+
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/*************************************************************************
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*
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* Startup Code (reset vector)
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@@ -215,10 +218,46 @@ WEAK(lowlevel_init)
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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2:
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+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
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+ bl fsl_ocram_init
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+#endif
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
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+ENTRY(fsl_ocram_init)
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+ mov x28, lr /* Save LR */
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+ bl fsl_clear_ocram
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+ bl fsl_ocram_clear_ecc_err
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+ mov lr, x28 /* Restore LR */
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+ ret
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+ENDPROC(fsl_ocram_init)
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+
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+ENTRY(fsl_clear_ocram)
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+/* Clear OCRAM */
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+ ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
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+ ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
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+ mov x2, #0
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+clear_loop:
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+ str x2, [x0]
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+ add x0, x0, #8
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+ cmp x0, x1
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+ b.lo clear_loop
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+ ret
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+ENDPROC(fsl_clear_ocram)
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+
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+ENTRY(fsl_ocram_clear_ecc_err)
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+ /* OCRAM1/2 ECC status bit */
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+ mov w1, #0x60
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+ ldr x0, =DCSR_SYS_DCFG_SBEESR2
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+ str w1, [x0]
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+ ldr x0, =DCSR_SYS_DCFG_MBEESR2
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+ str w1, [x0]
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+ ret
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+ENDPROC(fsl_ocram_init)
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+#endif
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+
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WEAK(smp_kick_all_cpus)
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/* Kick secondary cpus up by SGI 0 interrupt */
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mov x29, lr /* Save LR */
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--
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1.7.9.5
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