5e49c57956
1)Changes - Rebased the patches for linux-4.4.7 - Added patch to fix spi nor fifo and dma support - Added patch to configure watchdog barktime 2)Testing Tested on IPQ AP148 Board: a. NOR boot and NAND boot b. ethernet network and ath10k wifi c. ubi sysupgrade UnTested dwc3 usb has not been validated on IPQ board(AP148) 3)Known Issues: Once we flash ubi image on AP148, and if we reset the board, uboot on first boot creates PEB and LEB for dynamic sized partitions, which is incorrect and not what linux expects which causes errors when trying to mount rootfs. In order to test this, we can use the below steps: a. Flash the ubi image on board and don't reset the board b. load the kernel fit image in RAM and boot from there. Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
207 lines
6 KiB
Diff
207 lines
6 KiB
Diff
Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v3,10/13] clk: qcom: Add KPSS ACC/GCC driver
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From: Stephen Boyd <sboyd@codeaurora.org>
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X-Patchwork-Id: 6063201
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Message-Id: <1426920332-9340-11-git-send-email-sboyd@codeaurora.org>
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To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
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Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
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linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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Viresh Kumar <viresh.kumar@linaro.org>, <devicetree@vger.kernel.org>
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Date: Fri, 20 Mar 2015 23:45:29 -0700
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The ACC and GCC regions present in KPSSv1 contain registers to
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control clocks and power to each Krait CPU and L2. For CPUfreq
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purposes probe these devices and expose a mux clock that chooses
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between PXO and PLL8.
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Cc: <devicetree@vger.kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 ++
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.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 28 +++++++
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drivers/clk/qcom/Kconfig | 8 ++
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/kpss-xcc.c | 95 ++++++++++++++++++++++
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5 files changed, 139 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
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create mode 100644 drivers/clk/qcom/kpss-xcc.c
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--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
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+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
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@@ -21,10 +21,17 @@
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the register region. An optional second element specifies
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the base address and size of the alias register region.
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+- clock-output-names:
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+ Usage: optional
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+ Value type: <string>
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+ Definition: Name of the output clock. Typically acpuX_aux where X is a
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+ CPU number starting at 0.
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+
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Example:
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clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x02088000 0x1000>,
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<0x02008000 0x1000>;
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+ clock-output-names = "acpu0_aux";
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};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
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@@ -0,0 +1,28 @@
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+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
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+
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+PROPERTIES
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+
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+- compatible:
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+ Usage: required
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+ Value type: <string>
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+ Definition: should be one of:
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+ "qcom,kpss-gcc"
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+
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+- reg:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: base address and size of the register region
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+
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+- clock-output-names:
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+ Usage: required
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+ Value type: <string>
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+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
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+ an L2 cache auxiliary clock.
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+
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+Example:
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+
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+ l2cc: clock-controller@2011000 {
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+ compatible = "qcom,kpss-gcc";
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+ reg = <0x2011000 0x1000>;
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+ clock-output-names = "acpu_l2_aux";
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+ };
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -115,6 +115,14 @@
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Say Y if you want to support CPU frequency scaling on devices
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such as MSM8974, APQ8084, etc.
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+config KPSS_XCC
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+ tristate "KPSS Clock Controller"
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+ depends on COMMON_CLK_QCOM
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+ help
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+ Support for the Krait ACC and GCC clock controllers. Say Y
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+ if you want to support CPU frequency scaling on devices such
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+ as MSM8960, APQ8064, etc.
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+
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config KRAIT_CLOCKS
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bool
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select KRAIT_L2_ACCESSORS
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -9,6 +9,7 @@
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clk-qcom-y += clk-regmap-divider.o
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clk-qcom-y += clk-regmap-mux.o
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clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
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+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
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clk-qcom-y += clk-hfpll.o
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clk-qcom-y += reset.o
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clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
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--- /dev/null
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+++ b/drivers/clk/qcom/kpss-xcc.c
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@@ -0,0 +1,95 @@
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+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+
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+static const char *aux_parents[] = {
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+ "pll8_vote",
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+ "pxo",
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+};
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+
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+static unsigned int aux_parent_map[] = {
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+ 3,
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+ 0,
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+};
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+
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+static const struct of_device_id kpss_xcc_match_table[] = {
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+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
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+ { .compatible = "qcom,kpss-gcc" },
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+ {}
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+};
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+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
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+
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+static int kpss_xcc_driver_probe(struct platform_device *pdev)
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+{
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+ const struct of_device_id *id;
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+ struct clk *clk;
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+ struct resource *res;
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+ void __iomem *base;
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+ const char *name;
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+
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+ id = of_match_device(kpss_xcc_match_table, &pdev->dev);
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+ if (!id)
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+ return -ENODEV;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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+
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+ if (id->data) {
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+ if (of_property_read_string_index(pdev->dev.of_node,
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+ "clock-output-names", 0, &name))
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+ return -ENODEV;
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+ base += 0x14;
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+ } else {
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+ name = "acpu_l2_aux";
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+ base += 0x28;
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+ }
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+
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+ clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
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+ ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
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+ 0, aux_parent_map, NULL);
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+
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+ platform_set_drvdata(pdev, clk);
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+
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+ return PTR_ERR_OR_ZERO(clk);
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+}
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+
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+static int kpss_xcc_driver_remove(struct platform_device *pdev)
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+{
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+ clk_unregister_mux(platform_get_drvdata(pdev));
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+ return 0;
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+}
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+
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+static struct platform_driver kpss_xcc_driver = {
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+ .probe = kpss_xcc_driver_probe,
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+ .remove = kpss_xcc_driver_remove,
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+ .driver = {
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+ .name = "kpss-xcc",
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+ .of_match_table = kpss_xcc_match_table,
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+ },
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+};
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+module_platform_driver(kpss_xcc_driver);
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+
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+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
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+MODULE_LICENSE("GPL v2");
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+MODULE_ALIAS("platform:kpss-xcc");
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