e8890c6be0
This is tested and works on ubnt-erx. Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com> SVN-Revision: 47903
36 lines
1.1 KiB
Diff
36 lines
1.1 KiB
Diff
--- a/arch/mips/include/asm/mach-ralink/mt7621.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
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@@ -13,6 +13,9 @@
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#ifndef _MT7621_REGS_H_
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#define _MT7621_REGS_H_
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+#define MT7621_PALMBUS_BASE 0x1C000000
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+#define MT7621_PALMBUS_SIZE 0x03FFFFFF
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+
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#define MT7621_SYSC_BASE 0x1E000000
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#define SYSC_REG_CHIP_NAME0 0x00
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -204,6 +204,21 @@ void prom_soc_init(struct ralink_soc_inf
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mips_cm_probe();
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mips_cpc_probe();
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+ if (mips_cm_numiocu()) {
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+ /* mips_cm_probe() wipes out bootloader
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+ config for CM regions and we have to configure them
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+ again. This SoC cannot talk to pamlbus devices
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+ witout proper iocu region set up.
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+
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+ FIXME: it would be better to do this with values
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+ from DT, but we need this very early because
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+ without this we cannot talk to pretty much anything
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+ including serial.
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+ */
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+ write_gcr_reg0_base(MT7621_PALMBUS_BASE);
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+ write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | CM_GCR_REGn_MASK_CMTGT_IOCU0);
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+ }
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+
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if (!register_cps_smp_ops())
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return;
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if (!register_cmp_smp_ops())
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