f17be5617a
This updates the iProc PCIe driver to the version currently submitted for kernel 4.5. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 47688
62 lines
2.3 KiB
Diff
62 lines
2.3 KiB
Diff
From 199ff14100095d52cd1b232cc0f3b12f348b5b07 Mon Sep 17 00:00:00 2001
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From: Ray Jui <rjui@broadcom.com>
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Date: Tue, 15 Sep 2015 17:39:18 -0700
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Subject: [PATCH 143/147] PCI: iproc: Fix PCIe reset logic
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The current reset logic does not always properly reset the device. For
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example, in the case when the perst_b signal is already de-asserted in the
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bootloader, the current reset logic fails to trigger a proper assert ->
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de-assert reset sequence.
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Fix the issue by always triggering the proper reset sequence.
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Also explicitly select the desired reset source, i.e., perst_b, and reduce
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the wait time after the device comes out of reset from 250 ms to 100 ms,
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based on recommendation from the ASIC team.
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Tested-by: Vladimir Dreizin <vdreizin@broadcom.com>
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Tested-by: Darren Edamura <dedamura@broadcom.com>
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Signed-off-by: Ray Jui <rjui@broadcom.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Vladimir Dreizin <vdreizin@broadcom.com>
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Reviewed-by: Trac Hoang <trhoang@broadcom.com>
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Reviewed-by: Scott Branden <sbranden@broadcom.com>
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---
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drivers/pci/host/pcie-iproc.c | 15 ++++++++++-----
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1 file changed, 10 insertions(+), 5 deletions(-)
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--- a/drivers/pci/host/pcie-iproc.c
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+++ b/drivers/pci/host/pcie-iproc.c
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@@ -31,6 +31,8 @@
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#include "pcie-iproc.h"
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#define CLK_CONTROL_OFFSET 0x000
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+#define EP_PERST_SOURCE_SELECT_SHIFT 2
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+#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
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#define EP_MODE_SURVIVE_PERST_SHIFT 1
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#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
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#define RC_PCIE_RST_OUTPUT_SHIFT 0
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@@ -119,15 +121,18 @@ static void iproc_pcie_reset(struct ipro
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u32 val;
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/*
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- * Configure the PCIe controller as root complex and send a downstream
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- * reset
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+ * Select perst_b signal as reset source. Put the device into reset,
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+ * and then bring it out of reset
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*/
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- val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
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+ val = readl(pcie->base + CLK_CONTROL_OFFSET);
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+ val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
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+ ~RC_PCIE_RST_OUTPUT;
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writel(val, pcie->base + CLK_CONTROL_OFFSET);
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udelay(250);
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- val &= ~EP_MODE_SURVIVE_PERST;
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+
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+ val |= RC_PCIE_RST_OUTPUT;
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writel(val, pcie->base + CLK_CONTROL_OFFSET);
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- msleep(250);
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+ msleep(100);
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}
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static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
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