ca49bcadae
Instead of setting the l2c_aux_val variable in the board code make it possible to set these through device tree and make use of that. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 46129
81 lines
3.5 KiB
Diff
81 lines
3.5 KiB
Diff
From 1bc7c02e7f37ddfa09cb0db330ee8cd4034d6410 Mon Sep 17 00:00:00 2001
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From: Geert Uytterhoeven <geert+renesas@glider.be>
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Date: Thu, 7 May 2015 11:27:11 +0200
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Subject: [PATCH 1/4] ARM: l2c: Add support for the "arm, shared-override"
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property
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"CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
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Shareable attribute" states:
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"The default behavior of the cache controller with respect to the
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shareable attribute is to transform Normal Memory Non-cacheable
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transactions into:
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- cacheable no allocate for reads
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- write through no write allocate for writes."
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Depending on the system architecture, this may cause memory corruption
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in the presence of bus mastering devices (e.g. OHCI). To avoid such
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corruption, the default behavior can be disabled by setting the Shared
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Override bit in the Auxiliary Control register.
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Currently the Shared Override bit can be set only using C code:
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- by calling l2x0_init() directly, which is deprecated,
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- by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
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fields, but using values differing from 0/~0 is also deprecated.
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Hence add support for an "arm,shared-override" device tree property for
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the l2c device node. By specifying this property, affected systems can
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indicate that non-cacheable transactions must not be transformed.
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Then, it's up to the OS to decide. The current behavior is to set the
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"shared attribute override enable" bit, as there may exist kernel linear
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mappings and cacheable aliases for the DMA buffers, even if CMA is
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enabled.
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See also commit 1a8e41cd672f894b ("ARM: 6395/1: VExpress: Set bit 22 in
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the PL310 (cache controller) AuxCtlr register"):
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"Clearing bit 22 in the PL310 Auxiliary Control register (shared
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attribute override enable) has the side effect of transforming
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Normal Shared Non-cacheable reads into Cacheable no-allocate reads.
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Coherent DMA buffers in Linux always have a Cacheable alias via the
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kernel linear mapping and the processor can speculatively load
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cache lines into the PL310 controller. With bit 22 cleared,
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Non-cacheable reads would unexpectedly hit such cache lines leading
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to buffer corruption."
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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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---
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Documentation/devicetree/bindings/arm/l2cc.txt | 6 ++++++
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arch/arm/mm/cache-l2x0.c | 5 +++++
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2 files changed, 11 insertions(+)
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--- a/Documentation/devicetree/bindings/arm/l2cc.txt
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+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
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@@ -72,6 +72,12 @@ Optional properties:
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- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
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<1> (forcibly enable), property absent (retain settings set by
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firmware)
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+- arm,shared-override : The default behavior of the pl310 cache controller with
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+ respect to the shareable attribute is to transform "normal memory
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+ non-cacheable transactions" into "cacheable no allocate" (for reads) or
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+ "write through no write allocate" (for writes).
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+ On systems where this may cause DMA buffer corruption, this property must be
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+ specified to indicate that such transforms are precluded.
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Example:
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--- a/arch/arm/mm/cache-l2x0.c
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+++ b/arch/arm/mm/cache-l2x0.c
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@@ -1171,6 +1171,11 @@ static void __init l2c310_of_parse(const
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}
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}
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+ if (of_property_read_bool(np, "arm,shared-override")) {
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+ *aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
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+ *aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
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+ }
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+
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prefetch = l2x0_saved_regs.prefetch_ctrl;
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ret = of_property_read_u32(np, "arm,double-linefill", &val);
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