ef944dcb85
Also refresh 3.10 patches. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 37502
91 lines
2.8 KiB
Diff
91 lines
2.8 KiB
Diff
--- a/arch/arm/boot/dts/imx6q.dtsi
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+++ b/arch/arm/boot/dts/imx6q.dtsi
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@@ -382,6 +382,15 @@
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};
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};
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+ pcie: pcie@01ffc000 {
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+ #crtc-cells = <1>;
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+ compatible = "fsl,imx6q-pcie", "fsl,pcie";
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+ reg = <0x01ffc000 0x4000>;
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+ clocks = <&clks 144>, <&clks 189>;
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+ clock-names = "pcie_axi", "pcie_ref_125m";
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+ status = "disabled";
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+ };
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+
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ipu2: ipu@02800000 {
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#crtc-cells = <1>;
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compatible = "fsl,imx6q-ipu";
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--- a/arch/arm/mach-imx/Kconfig
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+++ b/arch/arm/mach-imx/Kconfig
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@@ -790,6 +790,8 @@ config SOC_IMX6Q
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bool "i.MX6 Quad/DualLite support"
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select ARCH_HAS_CPUFREQ
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select ARCH_HAS_OPP
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+ select ARCH_HAS_IMX_PCIE
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+ select ARCH_SUPPORTS_MSI
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select ARM_CPU_SUSPEND if PM
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select ARM_ERRATA_754322
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select ARM_ERRATA_764369 if SMP
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@@ -816,6 +818,10 @@ config SOC_IMX6Q
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help
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This enables support for Freescale i.MX6 Quad processor.
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+config IMX_PCIE
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+ bool "PCI Express support"
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+ select PCI
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+
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endif
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source "arch/arm/mach-imx/devices/Kconfig"
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--- a/arch/arm/mach-imx/Makefile
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+++ b/arch/arm/mach-imx/Makefile
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@@ -98,6 +98,8 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SMP) += headsmp.o platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
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+obj-$(CONFIG_IMX_PCIE) += pcie.o
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+obj-$(CONFIG_PCI_MSI) += msi.o
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ifeq ($(CONFIG_PM),y)
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obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -547,6 +547,12 @@ int __init mx6q_clocks_init(void)
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clk_register_clkdev(clk[ahb], "ahb", NULL);
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clk_register_clkdev(clk[cko1], "cko1", NULL);
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clk_register_clkdev(clk[arm], NULL, "cpu0");
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+ clk_register_clkdev(clk[pcie_axi_sel], "pcie_axi_sel", NULL);
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+ clk_register_clkdev(clk[axi], "axi", NULL);
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+ clk_register_clkdev(clk[pll6_enet], "pll6_enet", NULL);
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+ clk_register_clkdev(clk[pcie_ref], "pcie_ref", NULL);
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+ clk_register_clkdev(clk[pcie_ref_125m], "pcie_ref_125m", NULL);
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+ clk_register_clkdev(clk[pcie_axi], "pcie_axi", NULL);
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if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
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clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
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--- a/arch/arm/mach-imx/mxc.h
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+++ b/arch/arm/mach-imx/mxc.h
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@@ -151,6 +151,10 @@ extern unsigned int __mxc_cpu_type;
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# define cpu_is_mx53() (0)
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#endif
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+#ifdef CONFIG_SOC_IMX6Q
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+# define mxc_cpu_type __mxc_cpu_type
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+#endif
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+
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#ifndef __ASSEMBLY__
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static inline bool cpu_is_imx6dl(void)
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{
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--- a/arch/arm/include/asm/io.h
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+++ b/arch/arm/include/asm/io.h
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@@ -178,6 +178,9 @@ extern int pci_ioremap_io(unsigned int o
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*/
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#ifdef CONFIG_NEED_MACH_IO_H
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#include <mach/io.h>
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+#elif defined(CONFIG_SOC_IMX6Q) && defined(CONFIG_IMX_PCIE)
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+#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
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+#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
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#elif defined(CONFIG_PCI)
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#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
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#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
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