638 lines
23 KiB
C
638 lines
23 KiB
C
/*
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* AR6K Driver layer event handling (i.e. interrupts, message polling)
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*
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* Copyright (c) 2007 Atheros Communications Inc.
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* All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation;
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*
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* Software distributed under the License is distributed on an "AS
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* IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
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* implied. See the License for the specific language governing
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* rights and limitations under the License.
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*
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*
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*
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*/
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#include "a_config.h"
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#include "athdefs.h"
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#include "a_types.h"
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#include "AR6Khwreg.h"
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#include "a_osapi.h"
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#include "a_debug.h"
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#include "hif.h"
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#include "htc_packet.h"
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#include "ar6k.h"
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extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
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extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
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static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev);
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#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */
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/* completion routine for ALL HIF layer async I/O */
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A_STATUS DevRWCompletionHandler(void *context, A_STATUS status)
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{
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HTC_PACKET *pPacket = (HTC_PACKET *)context;
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COMPLETE_HTC_PACKET(pPacket,status);
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return A_OK;
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}
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/* mailbox recv message polling */
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A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
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A_UINT32 *pLookAhead,
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int TimeoutMS)
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{
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A_STATUS status = A_OK;
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int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
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AR_DEBUG_ASSERT(timeout > 0);
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AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
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while (TRUE) {
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if (pDev->GetPendingEventsFunc != NULL)
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{
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HIF_PENDING_EVENTS_INFO events;
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/* the HIF layer uses a special mechanism to get events, do this
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* synchronously */
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status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
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&events,
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NULL);
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if (A_FAILED(status))
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{
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
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break;
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}
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if (events.Events & HIF_RECV_MSG_AVAIL)
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{
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/* there is a message available, the lookahead should be valid now */
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*pLookAhead = events.LookAhead;
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break;
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}
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}
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else
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{
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/* this is the standard HIF way.... */
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/* load the register table */
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status = HIFReadWrite(pDev->HIFDevice,
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HOST_INT_STATUS_ADDRESS,
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(A_UINT8 *)&pDev->IrqProcRegisters,
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AR6K_IRQ_PROC_REGS_SIZE,
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HIF_RD_SYNC_BYTE_INC,
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NULL);
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if (A_FAILED(status))
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{
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
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break;
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}
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/* check for MBOX data and valid lookahead */
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if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX))
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{
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if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
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{
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/* mailbox has a message and the look ahead is valid */
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*pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
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break;
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}
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}
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}
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timeout--;
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if (timeout <= 0)
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{
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
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status = A_ERROR;
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/* check if the target asserted */
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if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
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/* target signaled an assert, process this pending interrupt
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* this will call the target failure handler */
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DevServiceDebugInterrupt(pDev);
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}
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break;
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}
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/* delay a little */
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msleep(DELAY_PER_INTERVAL_MS);
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AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout));
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}
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AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
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return status;
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}
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static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev)
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{
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A_STATUS status;
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A_UINT8 cpu_int_status;
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A_UINT8 regBuffer[4];
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
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cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
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pDev->IrqEnableRegisters.cpu_int_status_enable;
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AR_DEBUG_ASSERT(cpu_int_status);
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
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("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
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cpu_int_status));
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/* Clear the interrupt */
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pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
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/* set up the register transfer buffer to hit the register 4 times , this is done
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* to make the access 4-byte aligned to mitigate issues with host bus interconnects that
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* restrict bus transfer lengths to be a multiple of 4-bytes */
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/* set W1C value to clear the interrupt, this hits the register first */
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regBuffer[0] = cpu_int_status;
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/* the remaining 4 values are set to zero which have no-effect */
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regBuffer[1] = 0;
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regBuffer[2] = 0;
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regBuffer[3] = 0;
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status = HIFReadWrite(pDev->HIFDevice,
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CPU_INT_STATUS_ADDRESS,
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regBuffer,
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4,
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HIF_WR_SYNC_BYTE_FIX,
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NULL);
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AR_DEBUG_ASSERT(status == A_OK);
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return status;
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}
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static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
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{
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A_STATUS status;
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A_UINT8 error_int_status;
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A_UINT8 regBuffer[4];
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
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error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
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AR_DEBUG_ASSERT(error_int_status);
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
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("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
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error_int_status));
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if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
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/* Wakeup */
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
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}
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if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
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/* Rx Underflow */
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
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}
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if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
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/* Tx Overflow */
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
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}
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/* Clear the interrupt */
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pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
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/* set up the register transfer buffer to hit the register 4 times , this is done
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* to make the access 4-byte aligned to mitigate issues with host bus interconnects that
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* restrict bus transfer lengths to be a multiple of 4-bytes */
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/* set W1C value to clear the interrupt, this hits the register first */
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regBuffer[0] = error_int_status;
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/* the remaining 4 values are set to zero which have no-effect */
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regBuffer[1] = 0;
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regBuffer[2] = 0;
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regBuffer[3] = 0;
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status = HIFReadWrite(pDev->HIFDevice,
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ERROR_INT_STATUS_ADDRESS,
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regBuffer,
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4,
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HIF_WR_SYNC_BYTE_FIX,
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NULL);
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AR_DEBUG_ASSERT(status == A_OK);
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return status;
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}
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static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
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{
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A_UINT32 dummy;
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A_STATUS status;
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/* Send a target failure event to the application */
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
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if (pDev->TargetFailureCallback != NULL) {
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pDev->TargetFailureCallback(pDev->HTCContext);
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}
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/* clear the interrupt , the debug error interrupt is
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* counter 0 */
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/* read counter to clear interrupt */
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status = HIFReadWrite(pDev->HIFDevice,
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COUNT_DEC_ADDRESS,
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(A_UINT8 *)&dummy,
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4,
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HIF_RD_SYNC_BYTE_INC,
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NULL);
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AR_DEBUG_ASSERT(status == A_OK);
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return status;
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}
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static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
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{
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A_UINT8 counter_int_status;
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
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counter_int_status = pDev->IrqProcRegisters.counter_int_status &
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pDev->IrqEnableRegisters.counter_int_status_enable;
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AR_DEBUG_ASSERT(counter_int_status);
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
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("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
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counter_int_status));
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/* Check if the debug interrupt is pending */
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if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
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return DevServiceDebugInterrupt(pDev);
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}
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return A_OK;
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}
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/* callback when our fetch to get interrupt status registers completes */
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static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
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{
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AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
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A_UINT32 lookAhead = 0;
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A_BOOL otherInts = FALSE;
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
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do {
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if (A_FAILED(pPacket->Status)) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
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(" GetEvents I/O request failed, status:%d \n", pPacket->Status));
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/* bail out, don't unmask HIF interrupt */
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break;
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}
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if (pDev->GetPendingEventsFunc != NULL) {
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/* the HIF layer collected the information for us */
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HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer;
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if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
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lookAhead = pEvents->LookAhead;
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if (0 == lookAhead) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
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}
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}
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if (pEvents->Events & HIF_OTHER_EVENTS) {
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otherInts = TRUE;
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}
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} else {
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/* standard interrupt table handling.... */
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AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer;
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A_UINT8 host_int_status;
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host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
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if (host_int_status & (1 << HTC_MAILBOX)) {
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host_int_status &= ~(1 << HTC_MAILBOX);
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if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
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/* mailbox has a message and the look ahead is valid */
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lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
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if (0 == lookAhead) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
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}
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}
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}
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if (host_int_status) {
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/* there are other interrupts to handle */
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otherInts = TRUE;
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}
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}
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if (otherInts || (lookAhead == 0)) {
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/* if there are other interrupts to process, we cannot do this in the async handler so
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* ack the interrupt which will cause our sync handler to run again
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* if however there are no more messages, we can now ack the interrupt */
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
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(" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
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otherInts, lookAhead));
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HIFAckInterrupt(pDev->HIFDevice);
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} else {
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
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(" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
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lookAhead));
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/* lookahead is non-zero and there are no other interrupts to service,
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* go get the next message */
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pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, NULL);
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}
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} while (FALSE);
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/* free this IO packet */
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AR6KFreeIOPacket(pDev,pPacket);
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
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}
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/* called by the HTC layer when it wants us to check if the device has any more pending
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* recv messages, this starts off a series of async requests to read interrupt registers */
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A_STATUS DevCheckPendingRecvMsgsAsync(void *context)
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{
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AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
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A_STATUS status = A_OK;
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HTC_PACKET *pIOPacket;
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/* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
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* cause us to switch contexts */
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev));
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do {
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if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
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/* break the async processing chain right here, no need to continue.
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* The DevDsrHandler() will handle things in a loop when things are driven
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* synchronously */
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break;
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}
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/* first allocate one of our HTC packets we created for async I/O
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* we reuse HTC packet definitions so that we can use the completion mechanism
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* in DevRWCompletionHandler() */
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pIOPacket = AR6KAllocIOPacket(pDev);
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if (NULL == pIOPacket) {
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/* there should be only 1 asynchronous request out at a time to read these registers
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* so this should actually never happen */
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status = A_NO_MEMORY;
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AR_DEBUG_ASSERT(FALSE);
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break;
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}
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/* stick in our completion routine when the I/O operation completes */
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pIOPacket->Completion = DevGetEventAsyncHandler;
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pIOPacket->pContext = pDev;
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if (pDev->GetPendingEventsFunc) {
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/* HIF layer has it's own mechanism, pass the IO to it.. */
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status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
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(HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer,
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pIOPacket);
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} else {
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/* standard way, read the interrupt register table asynchronously again */
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status = HIFReadWrite(pDev->HIFDevice,
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HOST_INT_STATUS_ADDRESS,
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pIOPacket->pBuffer,
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AR6K_IRQ_PROC_REGS_SIZE,
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HIF_RD_ASYNC_BYTE_INC,
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pIOPacket);
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}
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
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} while (FALSE);
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
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return status;
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}
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/* process pending interrupts synchronously */
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static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing)
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{
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A_STATUS status = A_OK;
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A_UINT8 host_int_status = 0;
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A_UINT32 lookAhead = 0;
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev));
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/*** NOTE: the HIF implementation guarantees that the context of this call allows
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* us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
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* can block or switch thread/task ontexts.
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* This is a fully schedulable context.
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* */
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do {
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if (pDev->GetPendingEventsFunc != NULL) {
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HIF_PENDING_EVENTS_INFO events;
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/* the HIF layer uses a special mechanism to get events
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* get this synchronously */
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status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
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&events,
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NULL);
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if (A_FAILED(status)) {
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break;
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}
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if (events.Events & HIF_RECV_MSG_AVAIL) {
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lookAhead = events.LookAhead;
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if (0 == lookAhead) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
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}
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}
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if (!(events.Events & HIF_OTHER_EVENTS) ||
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!(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
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/* no need to read the register table, no other interesting interrupts.
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* Some interfaces (like SPI) can shadow interrupt sources without
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* requiring the host to do a full table read */
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break;
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}
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/* otherwise fall through and read the register table */
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}
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/*
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* Read the first 28 bytes of the HTC register table. This will yield us
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* the value of different int status registers and the lookahead
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* registers.
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* length = sizeof(int_status) + sizeof(cpu_int_status) +
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* sizeof(error_int_status) + sizeof(counter_int_status) +
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* sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
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* sizeof(hole) + sizeof(rx_lookahead) +
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* sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
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* sizeof(error_status_enable) +
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* sizeof(counter_int_status_enable);
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*
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*/
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status = HIFReadWrite(pDev->HIFDevice,
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HOST_INT_STATUS_ADDRESS,
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(A_UINT8 *)&pDev->IrqProcRegisters,
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AR6K_IRQ_PROC_REGS_SIZE,
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HIF_RD_SYNC_BYTE_INC,
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NULL);
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if (A_FAILED(status)) {
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break;
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}
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if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
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DevDumpRegisters(&pDev->IrqProcRegisters,
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&pDev->IrqEnableRegisters);
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}
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/* Update only those registers that are enabled */
|
|
host_int_status = pDev->IrqProcRegisters.host_int_status &
|
|
pDev->IrqEnableRegisters.int_status_enable;
|
|
|
|
if (NULL == pDev->GetPendingEventsFunc) {
|
|
/* only look at mailbox status if the HIF layer did not provide this function,
|
|
* on some HIF interfaces reading the RX lookahead is not valid to do */
|
|
if (host_int_status & (1 << HTC_MAILBOX)) {
|
|
/* mask out pending mailbox value, we use "lookAhead" as the real flag for
|
|
* mailbox processing below */
|
|
host_int_status &= ~(1 << HTC_MAILBOX);
|
|
if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
|
|
/* mailbox has a message and the look ahead is valid */
|
|
lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
|
|
if (0 == lookAhead) {
|
|
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
/* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
|
|
host_int_status &= ~(1 << HTC_MAILBOX);
|
|
}
|
|
|
|
} while (FALSE);
|
|
|
|
|
|
do {
|
|
|
|
/* did the interrupt status fetches succeed? */
|
|
if (A_FAILED(status)) {
|
|
break;
|
|
}
|
|
|
|
if ((0 == host_int_status) && (0 == lookAhead)) {
|
|
/* nothing to process, the caller can use this to break out of a loop */
|
|
*pDone = TRUE;
|
|
break;
|
|
}
|
|
|
|
if (lookAhead != 0) {
|
|
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
|
|
/* Mailbox Interrupt, the HTC layer may issue async requests to empty the
|
|
* mailbox...
|
|
* When emptying the recv mailbox we use the async handler above called from the
|
|
* completion routine of the callers read request. This can improve performance
|
|
* by reducing context switching when we rapidly pull packets */
|
|
status = pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, pASyncProcessing);
|
|
if (A_FAILED(status)) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* now handle the rest of them */
|
|
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
|
|
(" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
|
|
host_int_status));
|
|
|
|
if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
|
|
/* CPU Interrupt */
|
|
status = DevServiceCPUInterrupt(pDev);
|
|
if (A_FAILED(status)){
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
|
|
/* Error Interrupt */
|
|
status = DevServiceErrorInterrupt(pDev);
|
|
if (A_FAILED(status)){
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
|
|
/* Counter Interrupt */
|
|
status = DevServiceCounterInterrupt(pDev);
|
|
if (A_FAILED(status)){
|
|
break;
|
|
}
|
|
}
|
|
|
|
} while (FALSE);
|
|
|
|
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
|
|
*pDone, *pASyncProcessing, status));
|
|
|
|
return status;
|
|
}
|
|
|
|
|
|
/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
|
|
A_STATUS DevDsrHandler(void *context)
|
|
{
|
|
AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
|
|
A_STATUS status = A_OK;
|
|
A_BOOL done = FALSE;
|
|
A_BOOL asyncProc = FALSE;
|
|
|
|
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
|
|
|
|
|
|
while (!done) {
|
|
status = ProcessPendingIRQs(pDev, &done, &asyncProc);
|
|
if (A_FAILED(status)) {
|
|
break;
|
|
}
|
|
|
|
if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
|
|
/* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
|
|
asyncProc = FALSE;
|
|
/* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
|
|
* this has a nice side effect of blocking us until all async read requests are completed.
|
|
* This behavior is required on some HIF implementations that do not allow ASYNC
|
|
* processing in interrupt handlers (like Windows CE) */
|
|
}
|
|
|
|
if (asyncProc) {
|
|
/* the function performed some async I/O for performance, we
|
|
need to exit the ISR immediately, the check below will prevent the interrupt from being
|
|
Ack'd while we handle it asynchronously */
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
|
if (A_SUCCESS(status) && !asyncProc) {
|
|
/* Ack the interrupt only if :
|
|
* 1. we did not get any errors in processing interrupts
|
|
* 2. there are no outstanding async processing requests */
|
|
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
|
|
HIFAckInterrupt(pDev->HIFDevice);
|
|
}
|
|
|
|
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
|
|
return A_OK;
|
|
}
|
|
|
|
|