3f059f58db
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 38080
57 lines
2.6 KiB
Diff
57 lines
2.6 KiB
Diff
Subject: [v6,1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
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From: Sean Cross <xobs@kosagi.com>
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The i.MX6 has two general-purpose LVDS clocks that can be driven
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from a variety of sources. This patch adds a mux and a gate for
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both of these clocks.
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Signed-off-by: Sean Cross <xobs@kosagi.com>
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---
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arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++-
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2 files changed, 23 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
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index 9181a24..d94be84 100644
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -205,6 +205,11 @@ static const char *vpu_axi_sels[] = { "a
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static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
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"dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
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"ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
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+static const char *lvds_sels[] = {
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+ "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
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+ "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
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+ "pcie_ref", "sata_ref",
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+};
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enum mx6q_clks {
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dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
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@@ -238,7 +243,8 @@ enum mx6q_clks {
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pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
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ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
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sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
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- usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
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+ usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div,
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+ lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
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};
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static struct clk *clk[clk_max];
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@@ -340,6 +347,18 @@ int __init mx6q_clocks_init(void)
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base + 0xe0, 0, 2, 0, clk_enet_ref_table,
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&imx_ccm_lock);
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+ clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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+ clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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+
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+ /*
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+ * lvds1_gate and lvds2_gate are pseudo-gates. Both can be
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+ * independently configured as clock inputs or outputs. We treat
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+ * the "output_enable" bit as a gate, even though it's really just
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+ * enabling clock output.
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+ */
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+ clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
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+ clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
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+
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/* name parent_name reg idx */
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clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
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clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
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