openwrtv3/target/linux/lantiq/dts/P2812HNUFX.dtsi
John Crispin 2a390925df lantiq: Convert Zyxel P-2812HNU-FX and TP-Link TD-W8970 to support dwc2
Here the device tree entry for ifxhcd is listed as compatible with one
supported in dwc2 (after patching the dwc driver appropriately).

A second entry is added to support the second core of the hcd. This
entry is listed to be compatible with only dwc2. Done this way there
should be backwards support for both hcd drivers (ltq-hcd and dwc2)

Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com>

SVN-Revision: 44676
2015-03-11 17:08:32 +00:00

262 lines
5.8 KiB
Text

/include/ "vr9.dtsi"
/ {
chosen {
bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
};
memory@0 {
reg = <0x0 0x8000000>;
};
fpi@10000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,fpi", "simple-bus";
ranges = <0x0 0x10000000 0xEEFFFFF>;
reg = <0x10000000 0xEF00000>;
localbus@0 {
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
1 0 0x4000000 0x4000010>; /* addsel1 */
compatible = "lantiq,localbus", "simple-bus";
};
gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-xr9";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
interrupt-parent = <&icu0>;
interrupts = <166 135 66 40 41 42 38>;
#gpio-cells = <2>;
gpio-controller;
reg = <0xE100B10 0xA0>;
state_default: pinmux {
exin3 {
lantiq,groups = "exin3";
lantiq,function = "exin";
};
mdio {
lantiq,groups = "mdio";
lantiq,function = "mdio";
};
gphy-leds {
lantiq,groups = "gphy0 led1", "gphy1 led1",
"gphy0 led2", "gphy1 led2";
lantiq,function = "gphy";
lantiq,pull = <2>;
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
stp {
lantiq,groups = "stp";
lantiq,function = "stp";
lantiq,pull = <2>;
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
pci-in {
lantiq,groups = "req1";
lantiq,function = "pci";
lantiq,output = <0>;
lantiq,open-drain = <1>;
lantiq,pull = <2>;
};
pci-out {
lantiq,groups = "gnt1";
lantiq,function = "pci";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
pci_rst {
lantiq,pins = "io21";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <2>;
};
pcie-rst {
lantiq,pins = "io38";
lantiq,pull = <0>;
lantiq,output = <1>;
};
ifxhcd-rst {
lantiq,pins = "io33";
lantiq,pull = <0>;
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
nand_out {
lantiq,groups = "nand cle", "nand ale";
lantiq,function = "ebu";
lantiq,output = <1>;
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
nand_cs1 {
lantiq,groups = "nand cs1";
lantiq,function = "ebu";
lantiq,open-drain = <0>;
lantiq,pull = <0>;
};
};
};
eth@E108000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-net";
reg = < 0xE108000 0x3000 /* switch */
0xE10B100 0x70 /* mdio */
0xE10B1D8 0x30 /* mii */
0xE10B308 0x30 >; /* pmac */
interrupt-parent = <&icu0>;
interrupts = <73 72>;
lan: interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mac-address = [ 00 11 22 33 44 55 ];
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
};
stp: stp@E100BB0 {
compatible = "lantiq,gpio-stp-xway";
reg = <0xE100BB0 0x40>;
#gpio-cells = <2>;
gpio-controller;
lantiq,shadow = <0xffffff>;
lantiq,groups = <0x7>;
lantiq,dsl = <0x0>;
lantiq,phy1 = <0x0>;
lantiq,phy2 = <0x0>;
};
ifxhcd@E101000 {
status = "okay";
gpios = <&gpio 33 0>;
lantiq,portmask = <0x3>;
};
ifxhcd@E106000 {
status = "okay";
gpios = <&gpio 33 0>;
};
pci@E105400 {
status = "okay";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
compatible = "lantiq,pci-xway";
bus-range = <0x0 0x0>;
ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
reg = <0x7000000 0x8000 /* config space */
0xE105400 0x400>; /* pci bridge */
lantiq,bus-clock = <33333333>;
/*lantiq,external-clock;*/
lantiq,delay-hi = <0>; /* 0ns delay */
lantiq,delay-lo = <0>; /* 0.0ns delay */
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x7000 0 0 1 &icu0 30 1 // slot 14, irq 30
>;
gpio-reset = <&gpio 21 0>;
req-mask = <0x1>; /* GNT1 */
};
};
gphy-xrx200 {
compatible = "lantiq,phy-xrx200";
firmware1 = "lantiq/vr9_phy11g_a1x.bin"; /*VR9 1.1*/
firmware2 = "lantiq/vr9_phy11g_a2x.bin"; /*VR9 1.2*/
phys = [ 00 01 ];
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
reset {
label = "reset";
gpios = <&gpio 39 1>;
linux,code = <0x198>;
};
rfkill {
label = "rfkill";
gpios = <&gpio 1 1>;
linux,code = <0xf7>;
};
};
};