654bc380ec
keep default as 3.14, mt7621 gic need to be ported to 3.18 Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44349
257 lines
4.5 KiB
Text
257 lines
4.5 KiB
Text
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,mtk7628an-soc";
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cpus {
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cpu@0 {
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compatible = "mips,mips24KEc";
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};
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc@0 {
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compatible = "ralink,mt7620a-sysc";
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reg = <0x0 0x100>;
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};
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watchdog@120 {
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compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
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reg = <0x120 0x10>;
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resets = <&rstctrl 8>;
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reset-names = "wdt";
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interrupt-parent = <&intc>;
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interrupts = <24>;
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};
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intc: intc@200 {
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compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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resets = <&rstctrl 9>;
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reset-names = "intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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ralink,intc-registers = <0x9c 0xa0
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0x6c 0xa4
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0x80 0x78>;
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};
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memc@300 {
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compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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resets = <&rstctrl 20>;
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reset-names = "mc";
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interrupt-parent = <&intc>;
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interrupts = <3>;
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};
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gpio@600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
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reg = <0x600 0x100>;
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gpio0: bank@0 {
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reg = <0>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: bank@1 {
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reg = <1>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: bank@2 {
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reg = <2>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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spi@b00 {
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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resets = <&rstctrl 18>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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status = "disabled";
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};
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uartlite@c00 {
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compatible = "ns16550a";
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reg = <0xc00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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resets = <&rstctrl 12>;
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reset-names = "uartl";
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interrupt-parent = <&intc>;
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interrupts = <20>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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};
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};
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pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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};
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spi_pins: spi {
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spi {
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ralink,group = "spi";
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ralink,function = "spi";
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};
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};
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uart0_pins: uartlite {
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uart {
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ralink,group = "uart0";
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ralink,function = "uart";
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};
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};
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};
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rstctrl: rstctrl {
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compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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usbphy: usbphy {
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compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
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#phy-cells = <1>;
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resets = <&rstctrl 22>;
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reset-names = "host";
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};
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sdhci@10130000 {
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compatible = "ralink,mt7620-sdhci";
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reg = <0x10130000 4000>;
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interrupt-parent = <&intc>;
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interrupts = <14>;
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status = "disabled";
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};
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ehci@101c0000 {
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compatible = "ralink,rt3xxx-ehci";
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reg = <0x101c0000 0x1000>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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ohci@101c1000 {
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compatible = "ralink,rt3xxx-ohci";
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reg = <0x101c1000 0x1000>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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ethernet@10100000 {
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compatible = "ralink,rt5350-eth";
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reg = <0x10100000 10000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <5>;
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resets = <&rstctrl 21 &rstctrl 23>;
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reset-names = "fe", "esw";
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};
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esw@10110000 {
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compatible = "ralink,rt3050-esw";
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reg = <0x10110000 8000>;
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resets = <&rstctrl 23>;
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reset-names = "esw";
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interrupt-parent = <&intc>;
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interrupts = <17>;
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};
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pcie@10140000 {
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compatible = "mediatek,mt7620-pci";
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reg = <0x10140000 0x100
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0x10142000 0x100>;
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#address-cells = <3>;
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#size-cells = <2>;
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resets = <&rstctrl 26>;
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reset-names = "pcie0";
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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status = "disabled";
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
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>;
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pcie-bridge {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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};
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};
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};
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