3af779eb17
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.11, and Linux v3.12. This work mainly covers: * Ground work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family,and the Armada family. * Further updates to the mvebu MBus. * Work and ground work for enabling MSI on the Armada family. * some phy / mdio bus initialization related work. * Device tree binding documentation update. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39565
43 lines
2.1 KiB
Diff
43 lines
2.1 KiB
Diff
From 67f66e13d8a6da710d6df965021d92261083b584 Mon Sep 17 00:00:00 2001
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From: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Date: Wed, 25 Sep 2013 13:24:18 +0200
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Subject: [PATCH 089/203] ARM: mvebu: fix gated clock documentation
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The gated clock documentation referred only to the Orion SoC whereas
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it also applied for the Armada 370/XP SoC. This commit updates the
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introduction text and also the list of the compatible strings.
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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.../devicetree/bindings/clock/mvebu-gated-clock.txt | 14 ++++++++------
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1 file changed, 8 insertions(+), 6 deletions(-)
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--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
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+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
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@@ -1,10 +1,10 @@
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-* Gated Clock bindings for Marvell Orion SoCs
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+* Gated Clock bindings for Marvell EBU SoCs
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-Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save
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-some power. The clock consumer should specify the desired clock by having
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-the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
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-the corresponding clock gating control bit in HW to ease manual clock lookup
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-in datasheet.
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+Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be
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+gated to save some power. The clock consumer should specify the desired clock
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+by having the clock ID in its "clocks" phandle cell. The clock ID is directly
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+mapped to the corresponding clock gating control bit in HW to ease manual clock
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+lookup in datasheet.
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The following is a list of provided IDs for Armada 370:
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ID Clock Peripheral
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@@ -94,6 +94,8 @@ ID Clock Peripheral
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Required properties:
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- compatible : shall be one of the following:
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+ "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
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+ "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
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"marvell,dove-gating-clock" - for Dove SoC clock gating
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"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
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- reg : shall be the register address of the Clock Gating Control register
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