65 lines
2.3 KiB
Diff
65 lines
2.3 KiB
Diff
From: Miaoqing Pan <miaoqing@codeaurora.org>
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Date: Fri, 15 Jan 2016 18:17:21 +0800
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Subject: [PATCH] ath9k: fix data bus error on ar9300 and ar9580
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One crash issue be found on ar9300: RTC_RC reg read leads crash, leading
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the data bus error, due to RTC_RC reg write not happen properly.
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Warm Reset trigger in continuous beacon stuck for one of the customer for
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other chip, noticed the MAC was stuck in RTC reset. After analysis noticed
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DMA did not complete when RTC was put in reset.
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So, before resetting the MAC need to make sure there are no pending DMA
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transactions because this reset does not reset all parts of the chip.
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The 12th and 11th bit of MAC _DMA_CFG register used to do that.
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12 cfg_halt_ack 0x0
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0 DMA has not yet halted
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1 DMA has halted
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11 cfg_halt_req 0x0
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0 DMA logic operates normally
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1 Request DMA logic to stop so software can reset the MAC
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The Bit [12] of this register indicates when the halt has taken effect or
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not. the DMA halt IS NOT recoverable; once software sets bit [11] to
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request a DMA halt, software must wait for bit [12] to be set and reset
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the MAC.
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So, the same thing we implemented for ar9580 chip.
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Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
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---
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -1368,6 +1368,16 @@ static bool ath9k_hw_set_reset(struct at
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if (ath9k_hw_mci_is_enabled(ah))
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ar9003_mci_check_gpm_offset(ah);
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+ /* DMA HALT added to resolve ar9300 and ar9580 bus error during
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+ * RTC_RC reg read
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+ */
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+ if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
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+ REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
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+ ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
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+ 20 * AH_WAIT_TIMEOUT);
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+ REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
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+ }
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+
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REG_WRITE(ah, AR_RTC_RC, rst_flags);
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REGWRITE_BUFFER_FLUSH(ah);
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--- a/drivers/net/wireless/ath/ath9k/reg.h
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+++ b/drivers/net/wireless/ath/ath9k/reg.h
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@@ -34,8 +34,10 @@
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#define AR_CFG_SWRG 0x00000010
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#define AR_CFG_AP_ADHOC_INDICATION 0x00000020
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#define AR_CFG_PHOK 0x00000100
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-#define AR_CFG_CLK_GATE_DIS 0x00000400
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#define AR_CFG_EEBS 0x00000200
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+#define AR_CFG_CLK_GATE_DIS 0x00000400
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+#define AR_CFG_HALT_REQ 0x00000800
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+#define AR_CFG_HALT_ACK 0x00001000
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#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
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#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
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