011f2c26f1
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
137 lines
4.3 KiB
Diff
137 lines
4.3 KiB
Diff
From 716125d6733c9722b238f6d230579ead67a616bf Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 31 Mar 2016 18:38:20 -0700
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Subject: [PATCH] drm/vc4: Add support for gamma ramps.
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We could possibly save a bit of power by not requesting gamma
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conversion when the ramp happens to be 1:1, but at least if all the
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CRTCs are off the SRAM will be disabled.
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This should fix brightness sliders in a lot of fullscreen games.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit e582b6c7e7f9d0b1e30e8017e4082d3a9ede3310)
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 58 ++++++++++++++++++++++++++++++++++++++++++
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drivers/gpu/drm/vc4/vc4_regs.h | 6 +++++
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2 files changed, 64 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -49,6 +49,10 @@ struct vc4_crtc {
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/* Which HVS channel we're using for our CRTC. */
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int channel;
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+ u8 lut_r[256];
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+ u8 lut_g[256];
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+ u8 lut_b[256];
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+
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struct drm_pending_vblank_event *event;
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};
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@@ -147,6 +151,46 @@ static void vc4_crtc_destroy(struct drm_
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drm_crtc_cleanup(crtc);
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}
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+static void
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+vc4_crtc_lut_load(struct drm_crtc *crtc)
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+{
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+ struct drm_device *dev = crtc->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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+ u32 i;
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+
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+ /* The LUT memory is laid out with each HVS channel in order,
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+ * each of which takes 256 writes for R, 256 for G, then 256
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+ * for B.
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+ */
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+ HVS_WRITE(SCALER_GAMADDR,
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+ SCALER_GAMADDR_AUTOINC |
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+ (vc4_crtc->channel * 3 * crtc->gamma_size));
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+
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+ for (i = 0; i < crtc->gamma_size; i++)
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+ HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
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+ for (i = 0; i < crtc->gamma_size; i++)
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+ HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
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+ for (i = 0; i < crtc->gamma_size; i++)
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+ HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
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+}
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+
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+static void
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+vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
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+ uint32_t start, uint32_t size)
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+{
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+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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+ u32 i;
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+
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+ for (i = start; i < start + size; i++) {
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+ vc4_crtc->lut_r[i] = r[i] >> 8;
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+ vc4_crtc->lut_g[i] = g[i] >> 8;
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+ vc4_crtc->lut_b[i] = b[i] >> 8;
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+ }
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+
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+ vc4_crtc_lut_load(crtc);
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+}
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+
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static u32 vc4_get_fifo_full_level(u32 format)
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{
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static const u32 fifo_len_bytes = 64;
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@@ -260,8 +304,14 @@ static void vc4_crtc_mode_set_nofb(struc
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HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
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SCALER_DISPBKGND_AUTOHS |
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+ SCALER_DISPBKGND_GAMMA |
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(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
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+ /* Reload the LUT, since the SRAMs would have been disabled if
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+ * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
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+ */
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+ vc4_crtc_lut_load(crtc);
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+
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
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vc4_crtc_dump_regs(vc4_crtc);
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@@ -613,6 +663,7 @@ static const struct drm_crtc_funcs vc4_c
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.reset = drm_atomic_helper_crtc_reset,
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.atomic_duplicate_state = vc4_crtc_duplicate_state,
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.atomic_destroy_state = vc4_crtc_destroy_state,
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+ .gamma_set = vc4_crtc_gamma_set,
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};
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static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
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@@ -731,6 +782,7 @@ static int vc4_crtc_bind(struct device *
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primary_plane->crtc = crtc;
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vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
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vc4_crtc->channel = vc4_crtc->data->hvs_channel;
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+ drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
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/* Set up some arbitrary number of planes. We're not limited
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* by a set number of physical registers, just the space in
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@@ -771,6 +823,12 @@ static int vc4_crtc_bind(struct device *
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vc4_set_crtc_possible_masks(drm, crtc);
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+ for (i = 0; i < crtc->gamma_size; i++) {
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+ vc4_crtc->lut_r[i] = i;
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+ vc4_crtc->lut_g[i] = i;
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+ vc4_crtc->lut_b[i] = i;
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+ }
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+
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platform_set_drvdata(pdev, vc4_crtc);
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return 0;
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -390,6 +390,12 @@
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#define SCALER_DISPBASE2 0x0000006c
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#define SCALER_DISPALPHA2 0x00000070
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#define SCALER_GAMADDR 0x00000078
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+# define SCALER_GAMADDR_AUTOINC BIT(31)
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+/* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma
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+ * enabled.
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+ */
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+# define SCALER_GAMADDR_SRAMENB BIT(30)
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+
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#define SCALER_GAMDATA 0x000000e0
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#define SCALER_DLIST_START 0x00002000
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#define SCALER_DLIST_SIZE 0x00004000
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