231 lines
6.1 KiB
C
231 lines
6.1 KiB
C
/******************************************************************************
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**
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** FILE NAME : ifxmips_atm_danube.c
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** PROJECT : UEIP
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** MODULES : ATM
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**
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** DATE : 7 Jul 2009
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** AUTHOR : Xu Liang
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** DESCRIPTION : ATM driver common source file (core functions)
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 07 JUL 2009 Xu Liang Init Version
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*******************************************************************************/
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/*
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* ####################################
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* Head File
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* ####################################
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*/
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/*
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* Common Head File
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/proc_fs.h>
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#include <linux/init.h>
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#include <linux/ioctl.h>
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#include <linux/delay.h>
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/*
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* Chip Specific Head File
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*/
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#include "ifxmips_atm_core.h"
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#ifdef CONFIG_DANUBE
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#include "ifxmips_atm_fw_danube.h"
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#include "ifxmips_atm_fw_regs_danube.h"
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#include <lantiq_soc.h>
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#define EMA_CMD_BUF_LEN 0x0040
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#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
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#define EMA_DATA_BUF_LEN 0x0100
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#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
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#define EMA_WRITE_BURST 0x2
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#define EMA_READ_BURST 0x2
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static inline void reset_ppe(void);
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#define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
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#define IFX_PMU_MODULE_PPE_TC BIT(21)
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#define IFX_PMU_MODULE_PPE_EMA BIT(22)
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#define IFX_PMU_MODULE_PPE_QSB BIT(18)
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#define IFX_PMU_MODULE_TPE BIT(13)
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#define IFX_PMU_MODULE_DSL_DFE BIT(9)
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static inline void reset_ppe(void)
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{
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/*#ifdef MODULE
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unsigned int etop_cfg;
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unsigned int etop_mdio_cfg;
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unsigned int etop_ig_plen_ctrl;
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unsigned int enet_mac_cfg;
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etop_cfg = *IFX_PP32_ETOP_CFG;
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etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
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etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
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enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
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*IFX_PP32_ETOP_CFG &= ~0x03C0;
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// reset PPE
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ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
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*IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
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*IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
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*IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
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*IFX_PP32_ETOP_CFG = etop_cfg;
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#endif*/
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}
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/*
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* Description:
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* Download PPE firmware binary code.
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* Input:
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* src --- u32 *, binary code buffer
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* dword_len --- unsigned int, binary code length in DWORD (32-bit)
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* Output:
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* int --- 0: Success
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* else: Error Code
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*/
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static inline int danube_pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
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{
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volatile u32 *dest;
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if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
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|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
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return -1;
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if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
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IFX_REG_W32(0x00, CDM_CFG);
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else
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IFX_REG_W32(0x04, CDM_CFG);
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/* copy code */
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dest = CDM_CODE_MEMORY(0, 0);
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while ( code_dword_len-- > 0 )
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IFX_REG_W32(*code_src++, dest++);
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/* copy data */
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dest = CDM_DATA_MEMORY(0, 0);
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while ( data_dword_len-- > 0 )
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IFX_REG_W32(*data_src++, dest++);
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return 0;
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}
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static void danube_fw_ver(unsigned int *major, unsigned int *minor)
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{
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ASSERT(major != NULL, "pointer is NULL");
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ASSERT(minor != NULL, "pointer is NULL");
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*major = FW_VER_ID->major;
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*minor = FW_VER_ID->minor;
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}
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static void danube_init(void)
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{
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volatile u32 *p = SB_RAM0_ADDR(0);
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unsigned int i;
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ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
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IFX_PMU_MODULE_PPE_TC |
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IFX_PMU_MODULE_PPE_EMA |
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IFX_PMU_MODULE_PPE_QSB |
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IFX_PMU_MODULE_TPE |
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IFX_PMU_MODULE_DSL_DFE);
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reset_ppe();
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/* init ema */
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IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
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IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
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IFX_REG_W32(0x000000FF, EMA_IER);
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IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
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/* init mailbox */
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IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
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IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
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IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
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IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
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/* init atm tc */
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IFX_REG_W32(0x0000, DREG_AT_CTRL);
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IFX_REG_W32(0x0000, DREG_AR_CTRL);
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IFX_REG_W32(0x0, DREG_AT_IDLE0);
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IFX_REG_W32(0x0, DREG_AT_IDLE1);
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IFX_REG_W32(0x0, DREG_AR_IDLE0);
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IFX_REG_W32(0x0, DREG_AR_IDLE1);
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IFX_REG_W32(0x40, RFBI_CFG);
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IFX_REG_W32(0x1600, SFSM_DBA0);
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IFX_REG_W32(0x1718, SFSM_DBA1);
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IFX_REG_W32(0x1830, SFSM_CBA0);
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IFX_REG_W32(0x1844, SFSM_CBA1);
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IFX_REG_W32(0x14014, SFSM_CFG0);
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IFX_REG_W32(0x14014, SFSM_CFG1);
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IFX_REG_W32(0x1858, FFSM_DBA0);
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IFX_REG_W32(0x18AC, FFSM_DBA1);
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IFX_REG_W32(0x10006, FFSM_CFG0);
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IFX_REG_W32(0x10006, FFSM_CFG1);
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IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
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IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
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for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
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IFX_REG_W32(0, p++);
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}
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static void danube_shutdown(void)
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{
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}
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int danube_start(int pp32)
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{
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int ret;
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/* download firmware */
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ret = danube_pp32_download_code(
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danube_fw_bin, sizeof(danube_fw_bin) / sizeof(*danube_fw_bin),
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danube_fw_data, sizeof(danube_fw_data) / sizeof(*danube_fw_data));
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if ( ret != 0 )
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return ret;
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/* run PP32 */
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IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
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/* idle for a while to let PP32 init itself */
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udelay(10);
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return 0;
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}
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void danube_stop(int pp32)
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{
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IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
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}
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struct ltq_atm_ops danube_ops = {
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.init = danube_init,
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.shutdown = danube_shutdown,
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.start = danube_start,
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.stop = danube_stop,
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.fw_ver = danube_fw_ver,
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};
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#endif
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