This is mainly a bug fix for multi-core MIPS systems where L1 caches besides the primary do not get flushed.
The most obvious problem is data corruption on SATA and USB devices where read requests are typically larger than the cacheline size.
This may also fix ar71xx systems that suffer from similar data corruption but I have not tested if it does.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
