2 commits

Author	SHA1	Message	Date
Zoltan HERPAI	3db9d6e57d	intel-microcode: update to 20180312 ... - Update microcode for 24 CPU types - Implements IBRS/IBPB/STIPB support, Spectre-v2 mitigation for: Sandybridge, Ivy Bridge, Haswell, Broadwell, Skylake, Kaby Lake, Coffee Lake - Missing production updates: - Broadwell-E/EX Xeons (sig 0x406f1) - Anniedale/Morefield, Apollo Lake, Avoton, Cherry Trail, Braswell, Gemini Lake, Denverton - New Microcodes: - sig 0x00050653, pf_mask 0x97, 2018-01-29, rev 0x1000140 - sig 0x00050665, pf_mask 0x10, 2018-01-22, rev 0xe000009 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>	2018-03-21 23:24:09 +01:00
Zoltan HERPAI	01020bc74d	firmware: add microcode package for Intel ... Compiling the Intel microcode package results in a microcode.bin and a microcode-64.bin. As we can decide based on the subtarget which should be used, we'll only split the required .bin file with iucode-tool. x64 will get the intel-microcode-64.bin All other variants will get intel-microcode.bin The microcodes will be updated from preinit via a common script - that's the earliest place where we can do it. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>	2018-02-11 14:39:21 +01:00