Commit graph

5 commits

Author SHA1 Message Date
Matteo Croce
af4c2c041f add proper email addresses to the comment headers
SVN-Revision: 10709
2008-04-02 11:45:18 +00:00
Matteo Croce
c96a4d1808 Let authors holds copyright of the AR7 code (closes #2369)
SVN-Revision: 10708
2008-04-02 11:18:00 +00:00
Matteo Croce
9b93a436c7 vlynq: probe for an external clock first, needed to enable acx on the Leonardo board
SVN-Revision: 10707
2008-04-02 11:06:50 +00:00
Felix Fietkau
5dc134c542 Fix VLYNQ device enable for DG834Gv1
This patch allows VLYNQ devices on the DG834Gv1 to be successfully
enabled.

Currently the "__vlynq_enable_device" function attempts to set the VLYNQ
device clock divisor to values from 1 through 8 until a link is
successfully established. On the DG834Gv1 (but not the DG834Gv2),
setting the VLYNQ device clock divisor to 1 (full rate) results in all
further VLYNQ operations failing (including software reset), so the
device is never enabled. This patches changes the function to only
attempt divisors 2 through 8, and hence the device is successfully
enabled.

Signed-off-by: Nick Forbes <nick.forbes@huntsworth.com>

---------

SVN-Revision: 9656
2007-12-04 12:49:54 +00:00
Eugene Konev
3c4062a45f cleanup vlynq. drop vlynq-pci
SVN-Revision: 9143
2007-10-05 17:54:36 +00:00
Renamed from target/linux/ar7/files/arch/mips/ar7/vlynq.c (Browse further)