According to the author of the cpu temp driver, not all xrx200 boards
have a cpu temperature sensor. For that reason enable the sensor only
for tested boards.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Use the generic mtd-mac-address dts property to get a mac address from
flash instead of the lantiq specific one.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Use the same mac address increment in device tree source file and
userspace.
Don't add a mac address increment to either the only mtd mac-address or
to all mac-addresses.
Fix a typo in the TDW89X0.dtsi file to add an increment.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The device tree description misses some Ethernet ports and there was no
model specified for this board. In addition there was no switch
specific default configuration created.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Rename uboot environment partition on BT Home Hub 3A so that mac address
setting works correctly.
Also, the mac address field in the ath9k calibration data is not used,
and should not be referenced in the dts.
Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
Ethernet, ADSL2+ and LEDs are fully functional.
Supporting the two TAE ports and SIP gateway was not attempted.
The WiFi is unreliable, due to experimental support for rt35xx family
devices by the rt2800pci driver.
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
[rebase to LEDE HEAD]
[switch to normal image instead of brnboot image]
[remove not required pinmux child nodes keys, leds, ebu, exin, pci_in and pci_out]
[remove switch_rst pinmux child node (no support for hw reset in driver/setting a default GPIO value in DT]
[enable usage of the wireless LED]
[fixup mac address configuration]
Sgned-off-by: Mathias Kresin <dev@kresin.me>
The bootloader uses 30 MHz as the SPI frequency for flash on the Germany and
North America models, and 50 MHz for it on the worldwide model, but the Lantiq
SPI driver in OpenWrt and LEDE may access the flash differently such that
writes are capped at 20 MHz, leading to read errors reported on the worldwide
model at 30 MHz.
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
Acked-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
The EASY80920 is available with the A1X and the A2X chip version
depending on the board version. Add both firmware versions to device
tree and make the driver load the correct version depending on the chip
version.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The restart event code is used in LEDE to trigger a factory reset on
long press as well.
By using the power event code, the restart functionality can be used
without being prone to trigger a factory reset.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The RJ45 WAN port is used for xDSL as well as the IP101A.
The pins 1,2,3,6 of the RJ45 are connected to the IP101A and the
pins 4,5 are connected to the xdsl chip.
Drop the ip101a-rst node. It can't be controlled and is not required
at all.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The STP pinmux was initially added in assumption LAN2 led is driven by
it. It worked somehow because STP group and gphy0 led0 share the GPIO.
Do it the right way by adding the gphy0 led0 the gphy function.
According to the author, the SPI node is a copy & paste leftover. Which
makes sense since nothing is connected to the SPI bus on this device.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Use the brnboot partition layout as it is listed in the OpenWrt wiki
article for this board.
Configure the brnboot root selector for this device as well.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Cleanup the pinmux configuration by removing the unused spi node. Nothing is connected to the SPI bus on devices.
The stp_out pinmux child node covers the same GPIOs as the already used
stp group.
The same applies to the gphy-leds_out pinmux node and the "gphy0
led1" as well as "gphy1 led0" groups.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The only difference between the VG3503J profiles is the version of the
gphy firmware that gets loaded. This can be handled perfect fine in one
device tree source file.
Signed-off-by: Mathias Kresin <dev@kresin.me>
VGV7510KW2 with VRX288 v1.2 has brnboot 1.8 installed. Starting with
this brnboot version, the "GPHY Clock Source" isn't set anymore by
brnboot, with the result that xrx200-net fails to probe/initialize the
phys.
Use the phy clock source device tree binding to specify the clock source.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49284
Starting with kernel 4.4, the use of partitions as direct subnodes of the
mtd device is discouraged and only supported for backward compatiblity
reasons.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49280
Based on the vg3503j_gphy_led.sh script published in the VG3503J wiki
article, the OEM Firmware uses the following PHY led functionality:
gphy led 0: LINK/ACTIVITY
gphy led 1: LINK
gphy led 2: ACTIVITY
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49278
The VGV7510KW22 has the leds for LAN1-3 connected to pin1 of the phys
and the led for LAN4 connect to pin0 of the phy. This results with the
current configuration in a fast flashing LAN4 led as soon as a network
cable is connected. Something similar was reported on the forum[1] for
the VGV7519 as well.
Since it isn't predicable to which pin a (single) phy led is connected,
use the (default) pin1 functionality
Constant On: 10/100/1000MBit
Blink Fast: None
Blink Slow: None
Pulse: TX/RX
for all ethernet phy leds.
After checking pictures of all vr9 boards, it looks like only the VG3503J
has more than one led connected per phy. Using the phy led device tree
bindings to assign the functionality to the "additional" leds, the
VG3503J phy leds should behave as before.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
[1] https://forum.openwrt.org/viewtopic.php?pid=321523
SVN-Revision: 49270
Remove read-only flag on two partitions on BTHOMEHUBV3A:
uboot-config - otherwise fw_setenv command cannot be used.
ath9k-cal - so that ath9k calibration data can be copied
to the partition on a newly installed board.
Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
SVN-Revision: 49250
With the backport of the kernel 4.5 pinctrl-xway patches (3551609d &
826bca29) the pinmux group "spi" was splitted into "spi_di", "spi_do" &
"spi_clk". But the no longer existing group "spi" is still used by some
device tree source files.
This fixes the detection of the wireless chipset of the VGV7510KW22.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 48658
The stock u-boot doesn't disable unused flash banks. Therefore, the nand
driver tries to initialize a not connected NOR flash and the device
hangs on boot.
Workaround the issue by selecting the second flash bank (NAND).
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48657
All other SoC types are using "lantiq,sram" and "simple-bus" to ensure
that all child nodes are set up correctly during linux kernel
initialization (plat_of_setup(void) in arch/mips/lantiq/prom.c). Without
this some of sram child nodes might not be parsed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48548
This removes a lot of duplicate register and interrupt definitions by
moving the xrx200-net definition to vr9.dtsi and making all devices re-
use it.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48547
This adds basic support for TP-Link VR200v.
Currently the following parts are not working: FXO, Voice, DECT, WIFI (both)
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 48328
Re-defining the compatible property is not required since the correct
value is inherited from vr9.dtsi.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48295
Compared to the "old" driver:
- Each device must assign a pinctrl setting to the SPI node to allow the
new SPI driver to configure the SPI pins.
While here we are also using separate input and output settings so we
are independent of whether the bootloader configures the pins correctly.
- We use the new "compatible" strings to make the driver choose the
correct number of chip-selects for each SoC.
- The new driver starts counting the chip-selects at 1 (instead of 0, like
the old one did). Thus we have to adjust the devices accordingly.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48293
This allows devices to use SPI without having to re-define (and thus
duplicating) the whole SPI node.
By default SPI is disabled (as before) because only few devices need it.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48286
After the latest pinctrl backports there are only 50 (instead of 56 as
before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now
462, before it was 456). This means that any hardcoded GPIOs have to be
adjusted.
This broke the PCIe driver (which seems to be the only driver which uses
hardcoded GPIO numbers), it only reports:
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
pcie_rc_initialize link up failed!!!!!
To prevent more of these issues in the future we remove the hardcoded
PCIe reset GPIO definition and simply pass it via device-tree (like the
PCI driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48285
