Commit graph

11 commits

Author SHA1 Message Date
Florian Fainelli
3b92b4de00 I recently came across an ar7 device which has the vlynq hardwired so that the clocks are always generated by the remote device instead of the local one.
Upon initialization the current version of vlynq driver disables
remote clock generation and causes the entire bus to hang on my
device.

This patch adds support for detecting which device (local or remote)
is responsible of clock generation and implements clock
initialization based on detection result.

Signed-off-by: Antti Seppala <a.seppala at gmail.com>

SVN-Revision: 16049
2009-05-25 13:13:10 +00:00
Florian Fainelli
0fdecd35bd Treat vlynq external divisor just like automatic, fix comment about it, thanks sn9
SVN-Revision: 12467
2008-09-01 19:29:25 +00:00
Florian Fainelli
3ab8360af0 Fix divisor calculation and configuration from previous commit, thanks sn9
SVN-Revision: 12454
2008-09-01 11:49:57 +00:00
Florian Fainelli
3abe371efd Fix divisor settings for external devices like wireless devices, thanks sn9
SVN-Revision: 12443
2008-08-31 11:32:26 +00:00
Matteo Croce
78e07d75cd ar7: remove unneeded packed and array initialization
SVN-Revision: 10752
2008-04-07 01:30:07 +00:00
Matteo Croce
67dc179e05 vlynq: small fixes
SVN-Revision: 10711
2008-04-02 14:50:19 +00:00
Matteo Croce
af4c2c041f add proper email addresses to the comment headers
SVN-Revision: 10709
2008-04-02 11:45:18 +00:00
Matteo Croce
c96a4d1808 Let authors holds copyright of the AR7 code (closes #2369)
SVN-Revision: 10708
2008-04-02 11:18:00 +00:00
Matteo Croce
9b93a436c7 vlynq: probe for an external clock first, needed to enable acx on the Leonardo board
SVN-Revision: 10707
2008-04-02 11:06:50 +00:00
Felix Fietkau
5dc134c542 Fix VLYNQ device enable for DG834Gv1
This patch allows VLYNQ devices on the DG834Gv1 to be successfully
enabled.

Currently the "__vlynq_enable_device" function attempts to set the VLYNQ
device clock divisor to values from 1 through 8 until a link is
successfully established. On the DG834Gv1 (but not the DG834Gv2),
setting the VLYNQ device clock divisor to 1 (full rate) results in all
further VLYNQ operations failing (including software reset), so the
device is never enabled. This patches changes the function to only
attempt divisors 2 through 8, and hence the device is successfully
enabled.

Signed-off-by: Nick Forbes <nick.forbes@huntsworth.com>

---------

SVN-Revision: 9656
2007-12-04 12:49:54 +00:00
Eugene Konev
3c4062a45f cleanup vlynq. drop vlynq-pci
SVN-Revision: 9143
2007-10-05 17:54:36 +00:00